AD7822/AD7825/AD7829

–13–

REV. B

PARALLEL INTERFACE

The parallel interface of the AD7822, AD7825, and AD7829 is

eight bits wide. Figure 22 shows a timing diagram illustrating

the operational sequence of the AD7822/AD7825/AD7829

parallel interface. The multiplexer address is latched into the

AD7822/AD7825/AD7829 on the falling edge of the RD input.

The on-chip track/hold goes into hold mode on the falling

edge of CONVST and a conversion is also initiated at this

point. When the conversion is complete, the end of conversion

line (EOC) pulses low to indicate that new data is available in

the output register of the AD7822, AD7825, and AD7829. The

EOC pulse will stay logic low for a maximum time of 110 ns.

However, the EOC pulse can be reset high by a rising edge of

CONVST

EOC

CS

RD

DB0–DB7

A0–A2

VALID

DATA

NEXT

CHANNEL

ADDRESS

Figure 22. AD7822/AD7825/AD7829 Parallel Port Timing

RD. This EOC line can be used to drive an edge-triggered inter-

rupt of a microprocessor. CS and RD going low accesses the

8-bit conversion result. It is possible to tie CS permanently low

and use only RD to access the data. In systems where the part is

interfaced to a gate array or ASIC, this EOC pulse can be applied

to the CS and RD inputs to latch data out of the AD7822,

AD7825, and AD7829 and into the gate array or ASIC. This

means that the gate array or ASIC does not need any conver-

sion status recognition logic and it also eliminates the logic

required in the gate array or ASIC to generate the read signal

for the AD7822, AD7825, and AD7829.