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AD807 数据表(PDF) 12 Page - Analog Devices

部件名 AD807
功能描述  Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming
PDF  12 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD807 数据表(HTML) 12 Page - Analog Devices

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REV. A
–12–
AD807
USING THE AD807
Ground Planes
Use of one ground plane for connections to both analog and
digital grounds is recommended.
Power Supply Connections
Use of a 10
µF capacitor between V
CC and ground is recom-
mended. Care should be taken to isolate the +5 V power trace
to VCC2 (Pin 3). The VCC2 pin is used inside the device to pro-
vide the CLKOUT and DATAOUT signals.
Use of 0.1
µF capacitors between IC power supply and ground
is recommended. Power supply decoupling should take place as
close to the IC as possible. Refer to the schematic, Figure 21,
for recommended connections.
Transmission Lines
Use of 50
Ω transmission lines are recommended for PIN, NIN,
CLKOUT, and DATAOUT signals.
Terminations
Termination resistors should be used for PIN, NIN, CLKOUT,
and DATAOUT signals. Metal, thick film, 1% tolerance resistors
are recommended. Termination resistors for the PIN, NIN sig-
nals should be placed as close as possible to the PIN, NIN pins.
Connections from +5 V to load resistors for PIN, NIN,
CLKOUT, and DATAOUT signals should be individual, not
daisy chained. This will avoid crosstalk on these signals.
Loop Damping Capacitor, CD
A ceramic capacitor may be used for the loop damping capaci-
tor. Using a 0.15
µF, +20% capacitor for a damping factor of
five provides < 0.1 dB jitter peaking.
AD807 Output Squelch Circuit
A simple P-channel FET circuit can be used in series with the
Output Signal ECL Supply (VCC2, Pin 3) to squelch clock and
data outputs when SDOUT indicates a loss of signal (Figure
29). The VCC2 supply pin draws roughly 61 mA (14 mA for each
of 4 ECL loads, plus 5 mA for all 4 ECL output stages). This
means that selection of a FET with ON RESISTANCE of
0.5
Ω will affect the common mode of the ECL outputs by only
31 mV.
1
2
5
6
7
3
4
8
16
15
12
11
10
14
13
9
VEE
SDOUT
AVCC2
PIN
NIN
AVCC1
THRADJ
AVEE
DATAOUTN
DATAOUTP
CLKOUTN
CLKOUTP
VCC1
CF1
CF2
VCC2
AD807
TO VCC1, AVCC, AVCC2
P_FET
BYPASS
CAP
5V
Figure 29. Squelch Circuit Schematic
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Small Outline IC Package
(R-16A)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
1
16
9
8
0.0500 (1.27)
0.0160 (0.41)
8
°
0
°
0.0196 (0.50)
0.0099 (0.25)
x 45
°
0.0099 (0.25)
0.0075 (0.19)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
0.3937 (10.00)
0.3859 (9.80)



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