REV. B

AD826

–10–

THEORY OF OPERATION

The AD826 is a low cost, wide band, high performance dual

operational amplifier which can drive heavy capacitive and

resistive loads. It also achieves a constant slew rate, bandwidth

and settling time over its entire specified temperature range.

The AD826 (Figure 35) consists of a degenerated NPN differen-

tial pair driving matched PNPs in a folded-cascode gain stage.

The output buffer stage employs emitter followers in a class AB

amplifier which delivers the necessary current to the load while

maintaining low levels of distortion.

C

F

–IN

+IN

NULL 1

NULL 8

OUTPUT

+V

S

–V

S

Figure 35. Simplified Schematic

capacitive loads. With low capacitive loads, the gain from the

compensation node to the output is very close to unity. In this

compensation capacitance of the device. As the capacitive load

is increased, a pole is formed with the output impedance of the

contributes to the overall compensation capacitance, reducing

the unity gain bandwidth. As the load capacitance is further

increased, the bandwidth continues to fall, maintaining the

stability of the amplifier.

INPUT CONSIDERATIONS

circuits where the input to the AD826 will be subjected to

transient or continuous overload voltages exceeding the

± 6 V

maximum differential limit. This resistor provides protection for

the input transistors by limiting their maximum base current.

For high performance circuits, it is recommended that a “bal-

ancing” resistor be used to reduce the offset errors caused by

bias current flowing through the input and feedback resistors.

terminal. The offset voltage error will then be reduced by more

than an order of magnitude.

APPLYING THE AD826

The AD826 is a breakthrough dual amp that delivers precision

and speed at low cost with low power consumption. The AD826

offers excellent static and dynamic matching characteristics,

combined with the ability to drive heavy resistive and capacitive

loads.

As with all high frequency circuits, care should be taken to main-

tain overall device performance as well as their matching. The

following items are presented as general design considerations.

Circuit Board Layout

Input and output runs should be laid out so as to physically

isolate them from remaining runs. In addition, the feedback

resistor of each amplifier should be placed away from the

feedback resistor of the other amplifier, since this greatly

reduces inter-amp coupling.

Choosing Feedback and Gain Resistors

In order to prevent the stray capacitance present at each amplifier’s

summing junction from limiting its performance, the feedback

resistors should be

≤ 1 kΩ. Since the summing junction capaci-

tance may cause peaking, a small capacitor (1 pF–5 pF) may

should be avoided, because of their tendency to increase interlead

capacitance.

Power Supply Bypassing

Proper power supply decoupling is critical to preserve the

integrity of high frequency signals. In carefully laid out designs,

decoupling capacitors should be placed in close proximity to the

supply pins, while their lead lengths should be kept to a mini-

mum. These measures greatly reduce undesired inductive effects

on the amplifier’s response.

Though two 0.1

µF capacitors will typically be effective in

decoupling the supplies, several capacitors of different values

can be paralleled to cover a wider frequency range.