AD8320

–12–

REV. 0

75

Ω, a supply voltage of at least +10 V is required. To achieve

a signal level of +12 dBm (about 3.1 V p-p) into 75

Ω, a mini-

mum supply level of +5 V is required. However, for the lowest

possible distortion, the power supply voltage should be raised as

high as possible. In varying the power supply from +5 V to

+12 V, the quiescent current increases from 80 mA to 97 mA.

Careful attention must be paid to decoupling the power supply

pins. A 10

µF capacitor, located fairly close to the device, is

required to provide good decoupling for lower frequency signals.

In addition, five 0.1

µF decoupling capacitors should be located

close to each of the five power supply pins (7, 8, 9, 17 and 20).

A 0.1

µF capacitor must also be connected to the pin labeled

BYP (Pin 14), to provide decoupling to an internal node of the

device. All six ground pins should be connected to a low imped-

ance ground plane.

Alternative Power-Down Mode

As previously mentioned, the AD8320 can be put into a low

power sleep mode by pulling the

PD pin low. If lower power

consumption is required during power-down mode, an alternative

scheme can be used as shown in Figure 46.

75

AS103

GND

VCC

PD

* ADDITIONAL PINS AND DECOUPLING CAPACITORS

OMITTED FOR CLARITY

75

VCC+12V

+5V

VOUT

0.1 F

0.1 F

V1

V2

0.01 F

V2

V1

SDATA

CLK

DATEN

VOUT

VOCM

0.1 F

IRLML5103

0.1 F

D

G

S

J1

J2

J3

VDD

POWER-

DOWN

PD

V2

V1

SDATA

CLK

DATEN

POWER-

DOWN

PD

OUTPUT

QUIESCENT

CURRENT

10–12V

0V

0V

3–5V

0V

3–5V

0V

97mA

0mA

32mA

97mA

14

0.1 F

Figure 46. Alternative Power-Down Mode with Timing

A HEXFET power MOSFET (International Rectifier part num-

ber IRLML5103) is used to turn on and off the current to the

supply pins of the AD8320. Under normal operating conditions,

the gate (labeled POWER-DOWN) should be grounded. Pull-

ing the gate to within 2 V of the supply will open the switch and

reduce the current to the amplifier to zero.

In cable modem and cable telephony applications the modem

must always present an output impedance of 75

Ω to the line.

This forces the line driver to always present a 75

Ω impedance

to the diplexer. In this application, a single pole double throw

RF switch (AS103, Alpha Semiconductor) is used to switch in

an external 75

Ω impedance when the AD8320 is turned off.

This resistor then mimics the dynamic output impedance of the

AD8320. TTL or CMOS logic can be used to drive the two

voltages driving the RF switch (V1 and V2).

Before the AD8320 is turned back on again, the gain needs to

be set to a known level. This can be done by holding the

PD pin

of the AD8320 low after POWER-DOWN has gone high. While

PD is held low, the 8-bit serial data stream can be clocked into

the AD8320. During this time the quiescent current will in-

crease to 32 mA. However, this time period can be as small as

about 1

µs. In this mode the output settles about 45 ns after the

rising edge of

PD.

Alternatively, if

DATEN is held low as the AD8320 is powered

on, the device will power up in minimum gain. In this mode, the

output settles after about 200

µs. Note that for both cases, the

capacitor on VOCM has been reduced from 0.1

µF to 0.01 µF

to facilitate a faster turn-on time. All other capacitors in the

circuit should be connected as shown in Figure 45.