AD9042

REV. A

–21–

Equation 1:

SNR

= –20 log 2 πF









2

+









2

















1/2

= analog input frequency

= rms jitter of the encode (rms sum of encode source

and internal encode circuitry)

ε

= average DNL of the ADC

the ADC

Processing Gain

Processing gain is the improvement in signal-to-noise ratio

(SNR) gained through DSP processes. Most of this processing

gain is accomplished using the channelizer chips. These special

purpose DSP chips not only provide channel selection and

filtering but also provide a data rate reduction. Few, if any,

general purpose DSPs can accept and process data at

40.96 MSPS. The required rate reduction is accomplished

through a process called decimation. The term decimation rate

is used to indicate the ratio of input data rate to output data

rate. For example, if the input data rate is 40.96 MSPS and the

output data rate is 30 kSPS, then the decimation rate is 1365.

Large processing gains may be achieved in the decimation and

filtering process. The purpose of the channelizer, beyond

tuning, is to provide the narrowband filtering and selectivity that

traditionally has been provided by the ceramic or crystal filters

of a narrowband receiver. This narrowband filtering is the

source of the processing gain associated with a wideband

receiver and is simply the ratio of the passband to whole band

expressed in dB. For example, if a 30 kHz AMPS signal is

being digitized with an AD9042 sampling at 40.96 MSPS, the

ratio would be 0.030 MHz/20.48 MHz. Expressed in log form,

the processing gain is –10

× log (0.030 MHz / 20.48 MHz) or

28.3 dB!

Additional filtering and noise reduction techniques can be

achieved through DSP techniques; many applications do use

additional process gains through proprietary noise reduction

algorithms.

Overcoming Static Nonlinearities with Dither

Typically, high resolution data converters use multistage

techniques to achieve high bit resolution without large

comparator arrays that would be required if traditional “flash”

ADC techniques were employed. The multistage converter

typically provides better wafer yields meaning lower cost and

much lower power. However, since it is a multistage device,

certain portions of the circuit are used repetitively as the analog

input sweeps from one end of the converter range to the other.

Although the worst DNL error may be less than an LSB, the

repetitive nature of the transfer function can play havoc with low

level dynamic signals. Spurious signals for a full-scale input

may be –88 dBc, however 29 dB below full scale, these repeti-

tive DNL errors may cause spurious-free dynamic range (SFDR)

to fall to 80 dBc as shown in Figure 20.

A common technique for randomizing and reducing the effects

of repetitive static linearity is through the use of dither. The

purpose of dither is to force the repetitive nature of static

linearity to appear as if it were random. Then, the average

linearity over the range of dither will dominate SFDR

performance. In the AD9042, the repetitive cycle is every

15.625 mV p-p.

To insure adequate randomization, 5.3 mV rms is required;

this equates to a total dither power of –32.5 dBm. This will

randomize the DNL errors over the complete range of the

residue converter. Although lower levels of dither such as that

from previous analog stages will reduce some of the linearity

errors, the full effect will only be gained with this larger dither.

Increasing dither even more may be used to reduce some of the

global INL errors. However, signals much larger than the mVs

proposed here begin to reduce the usable dynamic range of the

converter.

Even with the 5.3 mV rms of noise suggested, SNR would be

limited to 36 dB if injected as broadband noise. To avoid this

problem, noise may be injected as an out-of-band signal. Typically,

this may be around dc but may just as well be at FS/2 or at

some other frequency not used by the receiver. The bandwidth

of the noise is several hundred kilohertz. By band-limiting and

controlling its location in frequency, large levels of dither may

be introduced into the receiver without seriously disrupting

receiver performance. The result can be a marked improvement

in the SFDR of the data converter.

Figure 23 shows the same converter shown earlier but with this

injection of dither (ref. Figure 20). Spurious-free dynamic

range is now 94 dBFS. Figure 21 and 24 show an SFDR sweep

before and after adding dither.

To more fully appreciate the improvement that dither can have

on performance, Figures 22 and 25 show a before-and-after

dither using additional data samples in the Fourier transform.

Increasing to 128k sample points lowers the noise floor of the

FFT; this simply makes it easier to “see” the dramatic reduction

in spurious levels resulting from dither.

14

13

12

11

9

16

15

10

8

1

2

3

4

7

6

5

AD600

A

A

REF

2.2k

Ω

1µF

0.1µF

39

Ω

390

Ω

16k

Ω

+15V

NC202

NOISE

DIODE

(NoiseCom)

+5V

–5V

1k

Ω

2k

Ω

OP27

OPTIONAL HIGH

POWER DRIVE

CIRCUIT

LOW CONTROL

(0–1 VOLT)

Figure 53. Noise Source (Dither Generator)

The simplest method for generating dither is through the use of

a noise diode (Figure 53). In this circuit, the noise diode

NC202 generates the reference noise that is gained up and

driven by the AD600 and OP27 amplifier chain. The level of

noise may be controlled by either presetting the control voltage

when the system is set up, or by using a digital-to-analog

converter (DAC) to adjust the noise level based on input signal

conditions. Once generated, the signal must be introduced to

the receiver strip. The easiest method is to inject the signal into

the drive chain after the last down conversion as shown in

Figure 54.