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AD9260AS 数据表(PDF) 8 Page - Analog Devices

部件名 AD9260AS
功能描述  High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate
PDF  36 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9260AS 数据表(HTML) 8 Page - Analog Devices

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REV. B
AD9260–SPECIFICATIONS
DIGITAL SPECIFICATIONS
Parameter
AD9260
Units
CLOCK
1 AND LOGIC INPUTS
High-Level Input Voltage
(DVDD = +5 V)
+3.5
V min
(DVDD = +3 V)
+2.1
V max
Low-Level Input Voltage
(DVDD = +5 V)
+1.0
V min
(DVDD = +3 V)
+0.9
V max
High-Level Input Current (VIN = DVDD)
±10
µA max
Low-Level Input Current (VIN = 0 V)
±10
µA max
Input Capacitance
5
pF typ
LOGIC OUTPUTS (with DRVDD = 5 V)
High-Level Output Voltage (IOH = 50
µA)
+4.5
V min
High-Level Output Voltage (IOH = 0.5 mA)
+2.4
V min
Low-Level Output Voltage
2 (I
OL = 0.3 mA)
+0.4
V max
Low-Level Output Voltage (IOL = 50
µA)
+0.1
V max
Output Capacitance
5
pF typ
LOGIC OUTPUTS (with DRVDD = 3 V)
High-Level Output Voltage (IOH = 50
µA)
+2.4
V min
Low-Level Output Voltage (IOL = 50
µA)
+0.7
V max
NOTES
1Since CLK is referenced to AVDD, +5 V logic input levels only apply.
2The AD9260 is not guaranteed to meet V
OL = 0.4 V max for standard TTL load of I OL = 1.6 mA.
Specifications subject to change without notice.
ANALOG INPUT
INPUT CLOCK
DATA OUTPUT
DAV
S1
S2
tDS
tH
tCH
tCL
tDAV
tDI
tC
READ
CS
tOD
tOE
Figure 4a. Timing Diagram
INPUT CLOCK
RESET
DAV
tRES-DAV
tCLK-DAV
Figure 4b.
RESET Timing Diagram
(AVDD = +5 V, DVDD = +5 V, TMIN to TMAX unless otherwise noted)



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