AD9774AS datasheet(2/24 Pages) AD

2 / 24 page

–2–

REV. B

AD9774–SPECIFICATIONS

DC SPECIFICATIONS

Parameter

Min

Typ

Max

Units

RESOLUTION

Bits

DC ACCURACY1

Integral Linearity Error (INL)

TA = +25°C

±4

LSB

TMIN to TMAX

Differential Nonlinearity (DNL)

TA = +25°C

±3

LSB

TMIN to TMAX

Monotonicity (12-Bit)

GUARANTEED OVER RATED SPECIFICATION TEMPERATURE RANGE

ANALOG OUTPUT

Offset Error

–0.025

+0.025

% of FSR

Gain Error (Without Internal Reference)

–7

±1

% of FSR

Gain Error (With Internal Reference)

+7.5

±1

+7.5

% of FSR

Full-Scale Output Current

Output Compliance Range

1.25

Output Resistance

100

Ω

Output Capacitance

REFERENCE OUTPUT

Reference Voltage

1.14

1.20

1.26

Reference Output Current

µA

REFERENCE INPUT

Input Compliance Range

0.1

1.25

Reference Input Resistance

Ω

TEMPERATURE COEFFICIENTS

Unipolar Offset Drift

ppm of FSR/

°C

Gain Drift (Without Internal Reference)

±50

ppm of FSR/

°C

Gain Drift (With Internal Reference)

±100

ppm of FSR/

°C

Reference Voltage Drift

±100

ppm of FSR/

°C

POWER SUPPLY

AVDD

Voltage Range

2.7

5.0

5.5

Analog Supply Current (IAVDD)

26.5

Analog Supply Current in SLEEP Mode (IAVDD)

3.2

PLLVDD

Voltage Range

2.7

5.0

5.5

Clock Multiplier Supply Current (IPLLVDD)13

DVDD

Voltage Range

2.7

5.0

5.5

Digital Supply Current at 5 V (IDVDD)

123.0

140.0

Digital Supply Current at 5 V in SNOOZE Mode (IDVDD)

42.0

50.0

Digital Supply Current at 3 V (IDVDD)

62.0

Nominal Power Dissipation

AVDD and DVDD at 3 V

415

AVDD and DVDD at 5 V6

1125

Power Supply Rejection Ratio (PSRR)

7 – AVDD

–0.2

+0.2

% of FSR/V

Power Supply Rejection Ratio (PSRR)7 – PLLVDD

–0.025

+0.025

% of FSR/V

Power Supply Rejection Ratio (PSRR)

7 – DVDD

–0.025

+0.025

% of FSR/V

OPERATING RANGE

–40

+85

°C

NOTES

1Measured at IOUTA driving a virtual ground.

2Nominal full-scale current, IOUTFS, is 32

× the I

REF current.

3Use an external amplifier to drive any external load.

4For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.

5Measured at f

CLOCK = 25 MSPS and fOUT = 1.01 MHz.

6Measured as unbuffered voltage output into 50

Ω R

LOAD at IOUTA and IOUTB, fCLOCK = 32 MSPS and fOUT = 12.8 MHz.

±5% power supply variation.

Specifications subject to change without notice.

(TMIN to TMAX, AVDD = +5 V, PLLVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted)

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