AD9830

REV. A

–3–

TIMING CHARACTERISTICS

Limit at

Parameter

(A Version)

Units

Test Conditions/Comments

20

ns min

MCLK Period

8

ns min

MCLK High Duration

8

ns min

MCLK Low Duration

1

8

ns min

WR

Rising Edge Before MCLK Rising Edge

1

8

ns min

WR

Rising Edge After MCLK Rising Edge

8

ns min

WR

Pulse Width

ns min

Duration Between Consecutive WR Pulses

5

ns min

Data/Address Setup Time

3

ns min

Data/Address Hold Time

1

8

ns min

FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge

1

8

ns min

FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge

ns min

RESET

Pulse Duration

NOTES

Guaranteed by design, but not production tested.

MCLK

WR

Figure 2. WR–MCLK Relationship

A0, A1, A2

DATA

WR

VALID DATA

VALID DATA

Figure 3. Writing to a Phase/Frequency Register

VALID DATA

VALID DATA

VALID DATA

MCLK

FSELECT

PSEL0, PSEL1

RESET

Figure 4. Control Timing

5%; AGND = DGND = 0 V, unless otherwise noted)