REV. 0

AD9841A/AD9842A

–21–

CCD

CCDIN

BUFFER

0.1 F

AD984xA

REGISTER

DATA

SERIAL

INTERFACE

DIGITAL

OUTPUTS

DIGITAL IMAGE

PROCESSING

ASIC

TIMING

GENERATOR

V-DRIVE

CCD

TIMING

CDS/CLAMP

TIMING

Figure 32. AD984xA System Applications Diagram

36

35

34

33

32

31

30

29

28

27

26

25

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

37

48 47 46 45 44

39 38

43 42 41 40

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

AUX1IN

AVSS

AUX2IN

AVDD2

BYP4

NC

CCDIN

BYP2

BYP1

AVDD1

AVSS

AVSS

NC

NC

(LSB) D0

D1

D2

D3

D4

D5

D6

D7

D8

(MSB) D9

AD9841A

0.1 F

0.1 F

0.1 F

0.1 F

0.1 F

0.1 F

3V

ANALOG SUPPLY

CCD SIGNAL

3V

ANALOG SUPPLY

10

DATA

OUTPUTS

3

SERIAL

INTERFACE

0.1 F

1.0 F

1.0 F

0.1 F

3V

ANALOG SUPPLY

8

CLOCK

INPUTS

0.1 F

0.1 F

3V

ANALOG SUPPLY

3V

DRIVER

SUPPLY

NC = NO CONNECT

Figure 33. AD9841A Recommended Circuit Configuration for CCD-Mode

APPLICATIONS INFORMATION

The AD9841A and AD9842A are complete Analog Front End

(AFE) products for digital still camera and camcorder appli-

cations. As shown in Figure 32, the CCD image (pixel) data is

buffered and sent to the AD984xA analog input through a series

input capacitor. The AD984xA performs the dc restoration,

CDS, gain adjustment, black level correction, and analog-to-

digital conversion. The AD984xA’s digital output data is then

processed by the image processing ASIC. The internal regis-

ters of the AD984xA—used to control gain, offset level, and other

functions—are programmed by the ASIC or microprocessor

through a 3-wire serial digital interface. A system timing gen-

erator provides the clock signals for both the CCD and the AFE.