REV. 0

AD9845A

–15–

SDATA

SCK

SL

A0 A1

A2

D0

D10 D0

D9

D0

D0

D7

RNW

0

0

D9

0

00

D0

1

217

35

34

27

26

16

6

5

4

3

44

45

51

63

62

57

56

50

68

...

...

...

...

...

...

...

...

10 BITS

ACG GAIN

D5

D0

D5

D0

D0

D5

D5

...

...

...

...

...

...

...

...

...

NOTES:

1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS AND INCREMENTING ONE ADDRESS AT A TIME.

2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED FOR EACH REGISTER.

3. ALL LOADED REGISTERS WILL BE SIMULTANEOUSLY UPDATED WITH THE RISING EDGE OF SL.

8 BITS

CLAMP LEVEL

10 BITS

CONTROL

11 BITS

OPERATION

6 BITS

PxGA GAIN0

6 BITS

PxGA GAIN1

6 BITS

PxGA GAIN2

6 BITS

PxGA GAIN3

Figure 23. Continuous Serial Write Operation to All Registers

SDATA

A0

A1

A2

D1

D0

D1

D2

D3

D4

D5

D0

D3

D2

D4

0

0

23

24

12

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

29

18

...

...

D5

0

01

D5

D5

D0

D0

RNW

SCK

SL

PxGA GAIN0

PxGA GAIN1

PxGA GAIN3

PxGA GAIN2

...

...

...

Figure 24. Continuous Serial Write Operation to All PxGA Gain Registers

Table II. Operation Register Contents (Default Value x000)

Optical Black Clamp

Reset

Power-Down Modes

Channel Selection

D10

D9

D8

D7

D6

D5

D4

D3 D2

D1 D0

0

*

0

*

0

*

1

**

0

*

0

Enable Clamping

0 Normal

0

0 Normal Power

0

0

CCD Mode

1

Disable Clamping

1 Reset All Registers

0

1 Fast Recovery

0

1

AUX1 Mode

to Default

1

0 Standby

1

0

AUX2 Mode

1

1 Total Power-Down

11

Test Only

*Must be set to zero.

**Set to one.

Table III. VGA Gain Register Contents (Default Value x096)

MSB

LSB

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Gain (dB)

X

0

0

010111112.0

••

••

••

1

1

11111110

35.965

1

1

11111111

36.0