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AD9853AS 数据表(PDF) 2 Page - Analog Devices |
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AD9853AS 数据表(HTML) 2 Page - Analog Devices |
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2 / 31 page  –2– REV. C AD9853–SPECIFICATIONS Parameter Temp Test Level Min Typ Max Units REF CLOCK INPUT CHARACTERISTICS Frequency Range 6 × REFCLK Disabled (+3.3 V Supply) Full IV 42 126 MHz 6 × REFCLK Enabled (+3.3 V Supply) Full IV 7 21 MHz 6 × REFCLK Disabled (+5 V Supply) Full IV 108 168 MHz 6 × REFCLK Enabled (+5 V Supply) Full IV 18 28 MHz Duty Cycle +25 °CIV 40 60 % Input Capacitance +25 °CV 3 pF Input Impedance +25 °C V 100 M Ω DAC OUTPUT CHARACTERISTICS Resolution 10 Bits Full-Scale Output Current +25 °C IV 5 10 20 mA Gain Error +25 °C I –10 +10 % FS Output Offset +25 °CI 10 µA Output Offset Temperature Coefficient Full V 50 nA/ °C Differential Nonlinearity +25 °C I 0.5 0.75 LSB Integral Nonlinearity +25 °C I 0.5 1.5 LSB Output Capacitance +25 °CV 5 pF Phase Noise @ 1 kHz Offset, 40 MHz AOUT 6 × REFCLK Enabled +25 °C V –100 dBc 6 × REFCLK Disabled +25 °C V –110 dBc Voltage Compliance Range +25 °C I –0.5 +1.5 V Wideband SFDR (Single Tone): 1 MHz AOUT +25 °C IV 62 68 dBc 20 MHz AOUT +25 °C IV 52 54 dBc 42 MHz AOUT +25 °C IV 48 50 dBc 65 MHz AOUT 1 +25 °C IV 42 44 dBc MODULATOR CHARACTERISTICS I/Q Offset +25 °CIV 48 dB Adjacent Channel Power +25 °C IV 44 dBm Error Vector Magnitude +25 °CIV 1 2 % In-Band Spurious Emission 5 MHz–42 MHz AOUT +25 °C IV 42 dBc 5 MHz–65 MHz AOUT 1 +25 °C IV 40 dBc Passband Amplitude Ripple +25 °CV ±0.3 dB TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency Full IV 25 MHz Minimum Clock Pulsewidth Low (tPWL) Full IV 10 ns Minimum Clock Pulsewidth High (tPWH) Full IV 10 ns Maximum Clock Rise/Fall Time Full IV 100 ns Minimum Data Setup Time (tDS) Full IV 10 ns Minimum Data Hold Time (tDH) Full IV 10 ns Minimum Clock Setup—Stop Condition (tCS) Full IV 10 ns Minimum Clock Hold—Start Condition (tCH) Full IV 10 ns RESET Minimum TXENABLE Low to RESET Low (tTR) Full IV 10 ns Minimum RESET High to Start Condition (tRH) Full IV 10 ns FEC ENABLE Minimum FEC ENABLE/DISABLE to TXENABLE High (tFH) Full IV 0 ns Minimum FEC ENABLE/DISABLE to TXENABLE Low (tFL) Full IV 0 ns (VS = +3.3 V 5%, RSET = 3.9 k , Reference Clock Frequency = 20.48 MHz with 6 REFCLK Enabled, Symbol Rate = 2.56 MS/s, = 0.25, unless otherwise noted) |
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