AD9854AST datasheet(13/44 Pages) AD

13 / 44 page

AD9854

–13–

REV. 0

TUNING

WORD

VCO

LOOP

FILTER

PHASE

COMPARATOR

REF

CLOCK

FREQUENCY

OUT

FILTER

AD9854

DDS

DIVIDE-BY-N

Figure 28a. Agile High-Frequency Synthesizer

PHASE

SPLITTER

0.8 TO

2.5 GHz

AD9854

QUADRATURE

DDS

DDS – LO

DDS

+ LO

36dB

TYPICAL

SSB

REJECTION

VOUT

AD8346 QUADRATURE

MODULATOR

COSINE (DC TO 70MHz)

SINE (DC TO 70MHz)

NOTES:

FLIP DDS QUADRATURE SIGNALS TO SELECT ALTERNATE SIDE-BAND.

ADJUST DDS SINE OR COSINE SIGNAL AMPLITUDE FOR GREATEST

SIDE-BAND SUPPRESSION.

DDS DAC OUTPUTS MUST BE LOW-PASS FILTERED PRIOR TO USE

WITH THE AD8346.

Figure 28b. Image Reject Mixer

LPF

AD9854

REFERENCE

CLOCK

SIN

COS

ANALOG MULTIPLIER

Analog Frequency Double Application

CLOCK OUT = 200MHz

LPF

SIN

LPF

AD9854

COS

REFERENCE

CLOCK

COMPARATORS

AOUT = 100MHz

Clock Frequency Doubler

PROCESSOR/

CONTROLLER

FPGA, ETC.

RSET

8-BIT PARALLEL OR

SERIAL PROGRAMMING

DATA AND CONTROL

SIGNALS

AD9854

CMOS LOGIC "CLOCK" OUT

REFERENCE

CLOCK

300MHz MAX DIRECT

MODE OR 15 TO 75MHz

MAX IN THE 4 –20

CLOCK

MULTIPLIER MODE

"I" DAC

NOTES:

IOUT = APPROX 20mA MAX WHEN RSET = 2k

SWITCH POSTION 1 PROVIDES COMPLEMENTARY

SINUSOIDAL SIGNALS TO THE COMPARATOR

TO PRODUCE A FIXED 50% DUTY CYCLE FROM

THE COMPARATOR.

SWITCH POSTION 2 PROVIDES THE SAME DUTY CYCLE

USING QUADRATURE SINUSOIDAL SIGNALS TO THE

COMPARATOR OR A DC THRESHOLD VOLTAGE TO

ALLOW SETTING OF THE COMPARATOR

DUTY CYCLE (DEPENDS ON THE "Q" DAC's

CONFIGURATION)

"Q" DAC OR

"CONTROL

DAC"

LOW-PASS

FILTER

LOW-PASS

FILTER

Figure 30. Frequency Agile Clock Generator Applications for the AD9854

REFERENCE

CLOCK

1:1 TRANSFORMER

I.E. MINI-CIRCUITS T1–1T

FILTER

DIFFERENTIAL

TRANSFORMER-COUPLED

OUTPUT

AD9854

DDS

IOUT

Figure 29. Differential Output Connection for Reduction of

Common-Mode Signals

AD9854AST 数据表(PDF) 13 Page - Analog Devices

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