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AD9856AST 数据表(PDF) 2 Page - Analog Devices

部件名 AD9856AST
功能描述  CMOS 200 MHz Quadrature Digital Upconverter
PDF  32 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9856AST 数据表(HTML) 2 Page - Analog Devices

  AD9856AST Datasheet HTML 1Page - Analog Devices AD9856AST Datasheet HTML 2Page - Analog Devices AD9856AST Datasheet HTML 3Page - Analog Devices AD9856AST Datasheet HTML 4Page - Analog Devices AD9856AST Datasheet HTML 5Page - Analog Devices AD9856AST Datasheet HTML 6Page - Analog Devices AD9856AST Datasheet HTML 7Page - Analog Devices AD9856AST Datasheet HTML 8Page - Analog Devices AD9856AST Datasheet HTML 9Page - Analog Devices Next Button
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–2–
REV. B
AD9856–SPECIFICATIONS
(VS = +3 V
5%, RSET = 3.9 k , External reference clock frequency = 10 MHz
with REFCLK Multiplier enabled at 20 ).
Test
AD9856
Parameter
Temp
Level
Min
Typ
Max
Units
REF CLOCK INPUT CHARACTERISTICS
Frequency Range
REFCLK Multiplier Disabled
Full
VI
5
200
1
MHz
REFCLK Multiplier Enabled at 4
×
Full
VI
5
50
MHz
REFCLK Multiplier Enabled at 20
×
Full
VI
5
10
MHz
Duty Cycle
+25
°CV
50
%
Input Capacitance
+25
°CV
3
pF
Input Impedance
+25
°C
V
100
M
DAC OUTPUT CHARACTERISTICS
Resolution
12
Bits
Full-Scale Output Current
5
10
20
mA
Gain Error
+25
°C
I
–10
+10
%FS
Output Offset
+25
°CI
10
µA
Differential Nonlinearity
+25
°C
V
0.5
LSB
Integral Nonlinearity
+25
°C
V
1
LSB
Output Capacitance
+25
°CV
5
pF
Phase Noise @ 1 kHz Offset, 40 MHz AOUT
REFCLK Multiplier Enabled at 20
×
+25
°C
V
–85
dBc/Hz
REFCLK Multiplier at 4
×
+25
°C
V
–100
dBc/Hz
REFCLK Multiplier Disabled
+25
°C
V
–110
dBc/Hz
Voltage Compliance Range
+25
°C
I
–0.5
1.5
V
Wideband SFDR:
1 MHz Analog Out
+25
°C
IV
70
dBc
20 MHz Analog Out
+25
°C
IV
65
dBc
42 MHz Analog Out
+25
°C
IV
60
dBc
65 MHz Analog Out
+25
°C
IV
55
dBc
80 MHz Analog Out
+25
°C
IV
50
dBc
Narrowband SFDR: (
±100 kHz Window)
70 MHz Analog Out
+25
°C
IV
80
dBc
MODULATOR CHARACTERISTICS
Adjacent Channel Power (CH Power = –6.98 dBm)
+25
°C
IV
50
dBm
Error Vector Magnitude
+25
°CIV
1
2
%
I/Q Offset
+25
°CIV
50
55
dB
Inband Spurious Emissions
+25
°C
IV
45
50
dBc
Pass Band Amplitude Ripple (DC to 80 MHz)
+25
°CV
±0.3
dB
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency
Full
IV
10
MHz
Minimum Clock Pulsewidth High (tPWH)
Full
IV
30
ns
Minimum Clock Pulsewidth Low (tPWL)
Full
IV
30
ns
Maximum Clock Rise/Fall Time
Full
IV
1
ms
Minimum Data Setup Time (tDS)
Full
IV
25
ns
Minimum Data Hold Time (tDH)
Full
IV
0
ns
Maximum Data Valid Time (tDV)
Full
IV
30
ns
Wake-Up Time
2
Full
IV
1
ms
Minimum RESET Pulsewidth High (tRH)
Full
IV
5
REFCLK
Cycles
CMOS LOGIC INPUTS
Logic “1” Voltage
+25
°C
I
+2.6
V
Logic “0” Voltage
+25
°C
I
+0.4
V
Logic “1” Current
+25
°CI
12
µA
Logic “0” Current
+25
°CI
12
µA
Input Capacitance
+25
°CV
3
pF



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