REV. 0

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a

AD9870

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 2001

IF Digitizing Subsystem

FUNCTIONAL BLOCK DIAGRAM

IFIN

FREF

AD9870

LNA

–16dB

LO

SYNTH

LO VCO AND

LOOP FILTER

CLK VCO AND

LOOP FILTER

SAMP CLOCK

SYNTHESIZER

DECIMATION

FILTER

CONTROL LOGIC

-

ADC

DAC AGC

SPI

VOLTAGE

REFERENCE

FORMATTING/SSI

DOUTA

DOUTB

FS

CLKOUT

VGA/

AAF

FEATURES

10 MHz–300 MHz Input Frequency

Baseband (I/Q) Digital Output

10 kHz–150 kHz Output Signal Bandwidth

12 dB SSB NF

> –1 dBm IIP3 (High IIP3 Mode)

25 dB Continuous AGC Range + 16 dB Gain Step

Support for LO and Sampling Clock Synthesis

Programmable Decimation Rate, Output Format, AAF

Cutoff, AGC and Synthesizer Settings

360

Input Impedance

2.7 V–3.6 V Supply Voltage

Low Current: 42 mA Typ (High IIP3 Mode),

30 mA Typ (Low IIP3, Fixed Gain Mode)

48-Lead LQFP Package (1.4 mm Thick)

APPLICATIONS

Portable and Mobile Radio Products

Digital UHF/VHF FDMA Products

TETRA

PRODUCT DESCRIPTION

The AD9870 is a general-purpose IF subsystem that digitizes a

low-level 10 MHz–300 MHz IF input with a bandwidth of up to

150 kHz. The signal chain of the AD9870 consists of a low-noise

amplifier, a mixer, a variable gain amplifier with integral antialias

filter, a bandpass sigma-delta analog-to-digital converter, and a

decimation filter with programmable decimation factor. An auto-

matic gain control (AGC) circuit provides the AD9870 with

25 dB of continuous gain adjustment. The high dynamic range

of the bandpass sigma-delta converter allows the AD9870 to

cope with blocking signals that are as much as 70 dB stronger

than the desired signal. Auxiliary blocks include clock and LO

synthesizers as well as a serial peripheral interface (SPI) port.

The SPI port programs numerous parameters of the AD9870,

including the synthesizer divide ratios, the AGC attack and decay

times, the AGC target signal level, the decimation factor, the

output data format, the 16 dB attenuator, and the bias currents of

several blocks. Reducing bias currents allows the user to reduce

power consumption at the expense of reduced performance.