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AD9875BST 数据表(PDF) 4 Page - Analog Devices |
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AD9875BST 数据表(HTML) 4 Page - Analog Devices |
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4 / 24 page ![]() REV. 0 –4– AD9875–SPECIFICATIONS Test Parameter Temp Level Min Typ Max Unit Tx PATH INTERFACE Maximum Input Nibble Rate, 2 × Interp. Full II 128 MHz Tx-Set Up Time (tSU) Full II 3.0 ns Tx-Hold Time (tHD) Full II 0 ns Rx PATH INTERFACE Maximum Output Nibble Rate Full I 110 MHz Rx-DataValid Time (tVT) Full II 3.0 ns Rx-Data Hold Time (tHT) Full II 1.5 ns CMOS LOGIC INPUTS Logic “1” Voltage Full II VDRVDD – 0.7 V Logic “0” Voltage Full II 0.4 V Logic “1” Current Full II 12 µA Logic “0” Current Full II 12 µA Input Capacitance 25 °C III 3 µF CMOS LOGIC OUTPUTS (1 mA Load) Logic “1” Voltage Full II VDRVDD – 0.6 V Logic “0” Voltage Full II 0.4 V Digital Output Rise/Fall Time Full II 1.5 2.5 ns POWER SUPPLY All Blocks Powered Up IS_TOTAL (Total Supply Current) Full I 262 288 mA IS_TOTAL (Tx_QUIET Pin Asserted) 25 °C III 172 mA Digital Supply Current (IDRVDD + IDVDD)25 °C III 77 mA Analog Supply Current (IAVDD)25 °C III 185 mA Power Consumption of Functional Blocks: Rx LPF 25 °C III 110 mA ADC and FPGA 25 °C III 55 mA Rx Reference 25 °C III 2 mA Interpolator 25 °C III 33 mA DAC 25 °C III 18 mA PLL-B 25 °C III 8 mA PLL-A 25 °C III 24 mA Voltage Regulator Controller 25 °C III 1 mA All Blocks Powered Down Supply Current IS, fOSCIN = 32 MHz Full II 19 22 mA Supply Current IS, fOSCIN Idle Full II 10 12 mA Power Supply Rejection Tx Path ( ∆V S = 10%) 25 °C III 62 dB Rx Path ( ∆V S = 10%) 25 °C III 54 dB SERIAL CONTROL BUS Maximum SCLK Frequency (fSCLK) Full II 25 MHz Clock Pulsewidth High (tPWH) Full II 18 ns Clock Pulsewidth Low (tPWL) Full II 18 ns Clock Rise/Fall Time Full II 1 ms Data/Chip-Select Setup Time (tDS) Full II 25 ns Data Hold Time (tDH) Full II 0 ns Data Valid Time (tDV) Full II 20 ns RECEIVE-TO-TRANSMIT ISOLATION (10 MHz, Full-Scale Sinewave Output/Output) Isolation: Tx Path to Rx Path, Gain = +36 dB 25 °C III –75 dB Isolation: Rx Path to Tx Path, Gain = –6 dB 25 °C III –70 dB VOLTAGE REGULATOR CONTROLLER Output Voltage (VFB with SI2301 Connected) Full I 1.25 1.30 1.35 V Line Regulation ( ∆V FB%/∆VDVDD% × 100%) 25 °C III 100 % Load Regulation ( ∆V FB/∆ILOAD)25°C III 60 m Ω Maximum Load Current (ILOAD) Full II 250 mA Specifications subject to change without notice. (continued) |
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