REV. B

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a

AD9884A

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 2000

100 MSPS/140 MSPS

Analog Flat Panel Interface

GENERAL DESCRIPTION

The AD9884A is a complete 8-bit 140 MSPS monolithic analog

interface optimized for capturing RGB graphics signals from

personal computers and workstations. Its 140 MSPS encode

rate capability and full-power analog bandwidth of 500 MHz

supports display resolutions of up to 1280

× 1024 (SXGA) at

75 Hz with sufficient input bandwidth to accurately acquire and

digitize each pixel.

To minimize system cost and power dissipation, the AD9884A

includes an internal +1.25 V reference, PLL to generate a pixel

clock from HSYNC, and programmable gain, offset and clamp

circuits. The user provides only a +3.3 V power supply, analog

input, and HSYNC signals. Three-state CMOS outputs may be

powered by a supply between 2.5 V and 3.3 V.

The AD9884A’s on-chip PLL generates a pixel clock from the

HSYNC input. Pixel clock output frequencies range from

FEATURES

140 MSPS Maximum Conversion Rate

500 MHz Analog Bandwidth

0.5 V to 1.0 V Analog Input Range

400 ps p-p PLL Clock Jitter

Power-Down Mode

3.3 V Power Supply

2.5 V to 3.3 V Three-State CMOS Outputs

Demultiplexed Output Ports

Data Clock Output Provided

Low Power: 570 mW Typical

Internal PLL Generates CLOCK from HSYNC

Serial Port Interface

Fully Programmable

Supports Alternate Pixel Sampling for Higher-

Resolution Applications

APPLICATIONS

RGB Graphics Processing

LCD Monitors and Projectors

Plasma Display Panels

Scan Converters

FUNCTIONAL BLOCK DIAGRAM

HSYNC

COAST

CLAMP

FILT

CKEXT

REFIN

CKINV

REFOUT

8

A/D

CLAMP

8

A/D

CLAMP

8

8

A/D

CLAMP

8

REF

8

8

8

8

8

8

SOGIN

0.15V

2

AD9884A

CLOCK

GENERATOR

SOGOUT

DATACK

HSOUT

CONTROL

20 MHz to 140 MHz. PLL clock jitter is typically 400 ps p-p

relative to the input reference. When the COAST signal is pre-

sented, the PLL maintains its output frequency in the absence

of HSYNC. A 32-step sampling phase adjustment is provided.

Data, HSYNC and Data Clock output phase relationships are

always maintained. The PLL can be disabled and an external

clock input provided as the pixel clock.

A clamp signal is generated internally or may be provided by the

user through the CLAMP input pin. This device is fully program-

mable via a two-wire serial port.

Fabricated in an advanced CMOS process, the AD9884A is

provided in a space-saving 128-lead MQFP surface mount plas-

tic package and is specified over a 0

°C to +70°C temperature

range.