AD9883SLASHPCB datasheet(12/24 Pages) AD

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AD9883

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Coast Timing

In most computer systems, the Hsync signal is provided con-

tinuously on a dedicated wire. In these systems, the COAST

input and function are unnecessary, and should not be used and

the pin should be permanently connected to the inactive state.

In some systems, however, Hsync is disturbed during the

Vertical Sync period (Vsync). In some cases, Hsync pulses

disappear. In other systems, such as those that employ Compos-

ite Sync (Csync) signals or embedded Sync-On-Green (SOG),

Hsync includes equalization pulses or other distortions during

Vsync. To avoid upsetting the clock generator during Vsync,

it is important to ignore these distortions. If the pixel clock

PLL sees extraneous pulses, it will attempt to lock to this new

frequency, and will have changed frequency by the end of the

Vsync period. It will then take a few lines of correct Hsync tim-

ing to recover at the beginning of a new frame, resulting in a

“tearing” of the image at the top of the display.

The COAST input is provided to eliminate this problem. It is

an asynchronous input that disables the PLL input and allows

the clock to free-run at its then-current frequency. The PLL can

free-run for several lines without significant frequency drift.

AD9883/PCB 数据表(PDF) 12 Page - Analog Devices