AD9887SLASHPCB datasheet(24/40 Pages) AD

24 / 40 page

REV. 0

–24–

AD9887

GENERAL TIMING DIAGRAMS (DIGITAL INTERFACE)

80%

20%

DLHT

Figure 28. Digital Output Rise and Fall Time

TCIH, RCIH

TCIP, RCIP

TCIL, RCIL

Figure 29. Clock Cycle/High/Low Times

VDIFF = 0V

TCCS

VDIFF = 0V

RX0

RX1

RX2

Figure 30. Channel-to-Channel Skew Timing

DATACK

(INTERNAL)

DATACK

(PIN)

tSKEW

DATA OUT

Figure 31. DVI Output Timing

TIMING MODE DIAGRAMS (DIGITAL INTERFACE)

FIRST

PIXEL

SECOND

PIXEL

THIRD

PIXEL

FOURTH

PIXEL

INTERNAL

ODCLK

DATACK

QE[23:0]

QO[23:0]

TST

Figure 32. 1 Pixel per Clock (DATACK Inverted)

FIRST

PIXEL

SECOND

PIXEL

THIRD

PIXEL

FOURTH

PIXEL

INTERNAL

ODCLK

DATACK

QE[23:0]

QO[23:0]

TST

Figure 33. 1 Pixels per Clock (DATACK Inverted)

FIRST PIXEL

SECOND PIXEL

THIRD PIXEL

FOURTH PIXEL

INTERNAL

ODCLK

DATACK

QE[23:0]

QO[23:0]

TST

Figure 34. 2 Pixel per Clock

FIRST PIXEL

SECOND PIXEL

THIRD PIXEL

FOURTH PIXEL

INTERNAL

ODCLK

DATACK

QE[23:0]

QO[23:0]

TST

Figure 35. 2 Pixels per Clock (DATACK Inverted)

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