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数据搜索系统，热门电子元器件搜索 |
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ADF4111BCP 数据表(PDF) 3 Page - Analog Devices |
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ADF4111BCP 数据表(HTML) 3 Page - Analog Devices |
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3 / 24 page  REV. 0 –3– ADF4110/ADF4111/ADF4112/ADF4113 Parameter B Version B Chips 2 Unit Test Conditions/Comments NOISE CHARACTERISTICS ADF4113 Phase Noise Floor 7 –171 –171 dBc/Hz typ @ 25 kHz PFD Frequency –164 –164 dBc/Hz typ @ 200 kHz PFD Frequency Phase Noise Performance 8 @ VCO Output ADF4110: 540 MHz Output 9 –91 –91 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency ADF4111: 900 MHz Output 10 –87 –87 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency ADF4112: 900 MHz Output 10 –90 –90 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency ADF4113: 900 MHz Output 10 –91 –91 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency ADF4111: 836 MHz Output 11 –78 –78 dBc/Hz typ @ 300 Hz Offset and 30 kHz PFD Frequency ADF4112: 1750 MHz Output 12 –86 –86 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency ADF4112: 1750 MHz Output 13 –66 –66 dBc/Hz typ @ 200 Hz Offset and 10 kHz PFD Frequency ADF4112: 1960 MHz Output 14 –84 –84 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency ADF4113: 1960 MHz Output 14 –85 –85 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency ADF4113: 3100 MHz Output 15 –86 –86 dBc/Hz typ @ 1 kHz Offset and 1 MHz PFD Frequency Spurious Signals ADF4110: 540 MHz Output 9 –97/–106 –97/–106 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency ADF4111: 900 MHz Output 10 –98/–110 –98/–110 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency ADF4112: 900 MHz Output 10 –91/–100 –91/–100 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency ADF4113: 900 MHz Output 10 –100/–110 –100/–110 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency ADF4111: 836 MHz Output 11 –81/–84 –81/–84 dBc typ @ 30 kHz/60 kHz and 30 kHz PFD Frequency ADF4112: 1750 MHz Output 12 –88/–90 –88/–90 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency ADF4112: 1750 MHz Output 13 –65/–73 –65/–73 dBc typ @ 10 kHz/20 kHz and 10 kHz PFD Frequency ADF4112: 1960 MHz Output 14 –80/–84 –80/–84 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency ADF4113: 1960 MHz Output 14 –80/–84 –80/–84 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency ADF4113: 3100 MHz Output 15 –80/–82 –82/–82 dBc typ @ 1 MHz/2 MHz and 1 MHz PFD Frequency NOTES 1Operating temperature range is as follows: B Version: –40 °C to +85°C. 2The B Chip specifications are given as typical values. 3This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency which is less than this value. 4AV DD = DVDD = 3 V; For AVDD = DVDD = 5 V, use CMOS-compatible levels. 5Guaranteed by design. 6T A = 25 °C; AV DD = DVDD = 3 V; P = 16; SYNC = 0; DLY = 0; RFIN for ADF4110 = 540 MHz; RFIN for ADF4111, ADF4112, ADF4113 = 900 MHz. 7The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). 8The phase noise is measured with the EVAL-ADF411XEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). SYNC = 0; DLY = 0 (See Table III). 9f REFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; Loop B/W = 20 kHz. 10f REFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz. 11f REFIN = 10 MHz; fPFD = 30 kHz; Offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; Loop B/W = 3 kHz. 12f REFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; Loop B/W = 20 kHz. 13f REFIN = 10 MHz; fPFD = 10 kHz; Offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz. 14f REFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; Loop B/W = 20 kHz. 15f REFIN = 10 MHz; fPFD = 1 MHz; Offset frequency = 1 kHz; fRF = 3100 MHz; N = 3100; Loop B/W = 20 kHz. Specifications subject to change without notice. TIMING CHARACTERISTICS1 Limit at TMIN to TMAX Parameter (B Version) Unit Test Conditions/Comments t1 10 ns min DATA to CLOCK Setup Time t2 10 ns min DATA to CLOCK Hold Time t3 25 ns min CLOCK High Duration t4 25 ns min CLOCK Low Duration t5 10 ns min CLOCK to LE Setup Time t6 20 ns min LE Pulsewidth NOTES 1Guaranteed by design but not production tested. Specifications subject to change without notice. (AVDD = DVDD = 3 V 10%, 5 V 10%; AVDD ≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 k ; TA = TMIN to TMAX unless otherwise noted) |
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