ADM1031 datasheet(21/32 Pages) AD

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REV. 0

ADM1031

–21–

CH1 100mV

CH3 50.0mV

CH2 5.00mV

CH4 50.0mV

M 4.00ms A CH1

–2.00mV

CH1

Tek PreVu

: 250mV

@: –258mV

Figure 20. Fan Speed Sensing Waveform at TACH/AIN Pin

FAN SPEED MEASUREMENT

The fan counter does not count the fan tach output pulses directly,

because the fan speed may be less than 1000 RPM and it would

take several seconds to accumulate a reasonably large and accu-

rate count. Instead, the period of the fan revolution is measured

by gating an on-chip 11.25 kHz oscillator into the input of an

8-bit counter. The fan speed measuring circuit is initialized

on the rising edge of a PWM high output if fan speed measure-

ment is enabled (Bit 2, 3 of Configuration Register 2 = 1). It

then starts counting on the rising edge of the second tach pulse

and counts for two fan tach periods, until the rising edge of the

fourth tach pulse, or until the counter overranges if the fan tach

period is too long. The measurement cycle will repeat until

monitoring is disabled. The fan speed measurement is stored in

the Fan Speed Reading register at address 0x08, 0x09.

The fan speed count is given by:

Count = (f

× 60)/R × N

where:

f = 11.25 kHz

R = Fan Speed in RPM.

N = Speed Range (Either 1, 2, 4, or 8)

The frequency of the oscillator can be adjusted to suit the

expected running speed of the fan by varying N, the Speed

Range. The oscillator frequency is set by Bits 7 and 6 of Fan

Characteristics Registers 1, 2 (0x20, 0x21) as shown in Table

XI. Figure 21 shows how the fan measurements relate to the

PWM_OUT pulse trains.

Table XI. Oscillator Frequencies

Oscillator

Bit 7

Bit 6

Frequency (kHz)

11.25

5.625

2.812

1.406

CLOCK

CONFIG 2

REG. BIT 2

FAN

INPUT

FAN

MEASUREMENT

PERIOD

START OF

MONITORING

CYCLE

Figure 21. Fan Speed Measurement

In situations where different output drive circuits are used for

fan drive, it may be desirable to invert the PWM drive signal.

Setting Bit 3 of Configuration Register 1 (0x00) to 1, inverts the

PWM_OUT signal. This makes the PWM_OUT pin high for

100% duty cycle. Bit 3 of Configuration Register 1 should gen-

erally be set to 1, when using an n-MOS device to drive the fan.

If using a p-MOS device, Bit 3 of Configuration Register 1

should be cleared to 0.

FAN FAULTS

The

FAN_FAULT output (Pin 8) is an active-low, open-drain

output used to signal fan failure to the system processor. Writing

a Logic 1 to Bit 4 of Configuration Register 1 (0x00) enables the

FAN_FAULT output pin. The FAN_FAULT output is enabled

by default. The

FAN_FAULT output asserts low only when

five consecutive interrupts are generated by the ADM1031 device

due to the fan running underspeed, or if the fan is completely

stalled. Note that the Fan Tach High Limit must be exceeded

by at least one before a

FAN_FAULT can be generated. For

example, if we are only interested in getting a

FAN_FAULT if

the fan stalls, then the fan speed value will be 0xFF for a failed

fan. Therefore, we should make the Fan Tach High Limit =

0xFE to allow

FAN_FAULT to be asserted after five consecu-

tive fan tach failures.

Figure 22 shows the relationship between

INT, FAN_FAULT,

and the PWM drive channel. The PWM_OUT channel is driv-

ing a fan at some PWM duty cycle, say 50%, and the fan’s tach

signal (or fan current for a 2-wire fan) is being monitored at the

TACH/AIN pin. Tach pulses are being generated by the fan,

during the high time of the PWM duty cycle train. The tach is

pulled high during the off time of the PWM train because the

fan is connected high-side to the n-MOS device.

Suppose the fan has twice previously failed its fan speed mea-

surement. Looking at Figure 22, PWM_OUT is brought high

for two seconds, to restart the fan if it has stalled. Sometime

later a third tach failure occurs. This is evident by the tach signal

being low during the high time of the PWM pulse, causing the Fan

Speed Reading register to reach its maximum count of 255.

Since the tach limit has been exceeded, an interrupt is gener-

ated on the

INT pin. The Fan Fault bit (Bit 1) of Interrupt

Status Register 1 (Register 0x02) will also be asserted. Once

the processor has acknowledged the

INT by reading the status

INT is cleared. PWM_OUT is then brought high

for another two seconds to restart the fan. Subsequent fan fail-

ures cause

INT to be reasserted and the PWM_OUT signal is

brought high for two seconds (fan spin-up default) each time to

restart the fan. Once the fifth tach failure occurs, the failure is

deemed to be catastrophic and the

FAN_FAULT pin is asserted

low. PWM_OUT is brought high to attempt to restart the fan.

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