ADM690A/ADM692A/ADM802L/M/ADM805L/M

–5–

REV. 0

BATTERY

SWITCHOVER

RESET

GENERATOR

WATCHDOG

TRANSITION DETECTOR

(1.6s)

4.65V*

1.25V

*4.4V FOR ADM692A/ADM802M/ADM805M

ADM690A

ADM692A

ADM802L

ADM802M

ADM805L

ADM805M

POWER FAIL

OUTPUT (PFO)

RESET

WATCHDOG

INPUT (WDI)

POWER FAIL

INPUT (PFI)

(RESET)

( ) = ADM805L/M ONLY

Figure 7. Functional Block Diagram

POWER FAIL RESET, RESET

RESET

is an active low output which provides a RESET signal

low. The nominal reset voltage threshold is 4.65 V (ADM690A/

ADM802L/ADM805L or 4.4 V ADM692A/ADM802M/

ADM805M.

above the reset threshold. This allows time for the power supply

and microprocessor to stabilize. On power-down, the RESET

the microprocessor is held in a stable shutdown condition.

The guaranteed minimum and maximum thresholds are as follows:

ADM690A/ADM802L/ADM805L: 4.5 V and 4.75 V

ADM692A: 4.25 V and 4.5 V.

ADM802L: 4.55 V and 4.7 V

ADM802M: 4.3 V and 4.45 V

The ADM805L and ADM805M contain an active high reset

output. This is the complement of RESET and is intended for

processors requiring an active high RESET signal.

The guaranteed minimum and maximum thresholds for the

ADM805 are:

ADM805L: 4.5 V and 4.75 V

ADM805M: 4.25 V and 4.5 V.

Watchdog Timer RESET, RESET

The watchdog timer circuit monitors the activity of the micro-

processor in order to check that it is not stalled in an indefinite

loop. An output line on the processor is used to toggle the

Watchdog Input (WDI) line. If this line is not toggled within

1.6 seconds, a RESET pulse is generated. The watchdog

timeout period restarts with each transition on the WDI pin. To

ensure that the watchdog timer does not time out, either a

high-to-low or low-to-high transition on the WDI pin must

occur at or less than the minimum timeout period. If WDI

remains permanently either high or low, reset pulses will be

issued after each timeout period (1.6 s). The watchdog monitor

can be deactivated by floating the Watchdog Input (WDI) or by

connecting it to midsupply.

+5V

0V

+5V

0V

+5V

0V

+5V

0V

0V

3.0V

3.0V

RESET

RESET

PFO

Figure 8. Timing Diagram

BATTERY SWITCHOVER SECTION

PMOS transistor switch. This switch has a typical on-resistance

of less than 1

Ω and can supply up to 100 mA at the V

OUT

may require instantaneous currents of greater than 100 mA. If

this is the case, then a bypass capacitor should be connected to

RAM. A capacitance value of 0.1

µF or greater may be used.

A 9

Ω MOSFET switch connects the V

during battery backup. This MOSFET has very low input-to-

output differential (dropout voltage) at the low current levels

required for battery backup of CMOS RAM or other low power

CMOS circuitry. The supply current in battery backup is

typically 0.05

µA.

Typically 3 V batteries are used as the backup supply. High

value capacitors, either standard electrolytic or the farad size

double layer capacitors, can also be used for short-term memory

back up. A small charging current of typically 10 nA (0.1

µA

maintaining rechargeable batteries in a fully charged condition.

This extends the life of the back up battery by compensating for

its self discharge current. Also note that this current poses no

problem when lithium batteries are used for back up since the

maximum charging current (0.1

µA) is safe for even the smallest

lithium cells.