ADMC201AP datasheet(3/15 Pages) AD

3 / 15 page

ADMC201

REV. B

–3–

Table I. Timing Specifications (VDD = 5 V,

5%; TA = –40 C to +85 C)

Number

Symbol

Timing Requirements

Min

Max

Units

1tperclk

CLK Period

160

2tpwhclk

CLK Pulsewidth, High

3tpwlclk

CLK Pulsewidth, Low

4tsucsb_wrb

CS Low before Falling Edge of WR

0ns

5tsuaddr_wrb

ADDR Valid before Falling Edge of

0ns

6tsudata_wrb

DATA Valid before Rising Edge of

7thdwrb_data

DATA Hold after Rising Edge of

4.5

8thdwrb_addr

ADDR Hold after Rising Edge of

4.5

9thdwrb_csb

CS Hold after Rising Edge of WR

4.5

tpwlwrb

WR Pulsewidth, Low

tpwhwrb

WR Pulsewidth, High

thdwrb_clk_h

WR Low after Rising Edge of CLK

tsuwrb_clk_h

WR High before Rising Edge of CLK

tsuwrb_clk_l

WR High before Falling Edge of CLK

thdclk_wrb_l

WR High after Falling Edge of CLK

tsucsb_rdb

CS Low before Falling Edge of RD

0ns

tsuaddr_rdb

ADDR Valid before Falling Edge of

0ns

thdrdb_addr

ADDR Hold after Rising Edge of

0ns

thdrdb_csb

CS Hold after Rising Edge of RD

0ns

tpwlrdb

RD Pulsewidth, Low

tpwhrdb

RD Pulsewidth, High

tsurdb_clk_h

RD Low before Rising Edge of CLK

7.5

thdrdb_clk_h

RD Low after Rising Edge of CLK

7.5

tpwlresetb

RESET Pulsewidth, Low

× t

perclk

NOTE

1All WRITES to the ADMC201 must occur within 1 System Clock Cycle (0 wait states).

Number

Symbol

Switching Characteristics

Min

Max

Units

tdlyrdb_data

DATA Valid after Falling Edge of

thdrdb_data

DATA Hold after Rising Edge of

0ns

tpwh_pio

Digital I/O Pulsewidth, High

× tperclk

tpwl_pio

Digital I/O Pulsewidth, Low

× tperclk

CLK

Figure 1. Clock Input Timing

RESET

CLK

Figure 2. Reset Input Timing

CLK

A0–A3

DATA

NOTE:

ALL WRITES TO THE ADMC201 MUST OCCUR WITHIN

ONE SYSTEM CLOCK CYCLE (i.e., 0 WAIT STATES)

Figure 3. Write Cycle Timing Diagram

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