ADMC328 datasheet(21/32 Pages) AD

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ADMC328

–21–

REV. B

When the DRIB data receive line of SPORT1 is selected as

the data receive line (MODECTRL [4] = 1), the PIO4/DRIA

line may be used as a general purpose PIO pin. When the DRIA

data receive line of SPORT1 is selected as the data receive line

(MODECTRL [4] = 0, the PIO2/DRIB line may be used as a

general-purpose PIO pin.

The functionality of the PIO6/CLKOUT, PIO7/AUX1, and

PIO8/AUX0 pins may be selected on a pin-by-pin basis as desired.

PIO Registers

The configuration of all registers of the PIO system is shown at

the end of the data sheet.

INTERRUPT CONTROL

The ADMC328 can respond to 16 different interrupt sources,

some of which are generated by internal DSP core interrupts

and others from the motor control peripherals. The DSP core

interrupts include the following:

A Peripheral (or IRQ2) Interrupt.

A SPORT1 Receive (or IRQ0) and a SPORT1 Transmit (or

IRQ1) Interrupt.

Two Software Interrupts.

An Interval Timer Time-Out Interrupt.

The interrupts generated by the motor control peripherals

include:

A PWMSYNC Interrupt.

Nine Programmable Input/Output (PIO) Interrupts.

A PWM Trip Interrupt.

The core interrupts are internally prioritized and individually

maskable. All peripheral interrupts are multiplexed into the

DSP core through the peripheral (IRQ2) interrupt.

The PWMSYNC interrupt is triggered by a low-to-high

transition on the PWMSYNC pulse. The PWMTRIP interrupt

is triggered on a high-to-low transition on the PWMTRIP pin,

an overcurrent on the ISENSE pin, or by writing to the PWMSWT

to-low or low-to-high) on the PIO lines.

The ADMC328 interrupt control system is configured and

controlled by the IFC, IMASK, and ICNTL registers of the

DSP core and by the IRQFLAG register for the PWMSYNC

and PWMTRIP interrupts. PIO interrupts are enabled and dis-

abled by the PIOINTEN0 and PIOINTEN1 registers.

Table IX. Interrupt Vector Addresses

Interrupt Vector

Interrupt Source

Address

PWMTRIP

0x002C (Highest Priority)

Peripheral Interrupt (IRQ2)

0x0004

PWMSYNC

0x000C

PIO

0x0008

Software Interrupt 1

0x0018

Software Interrupt 0

0x001C

SPORT1 Transmit Interrupt (or IRQ1) 0x0020

SPORT1 Receive Interrupt (or IRQ0)

0x0024

Timer

0x0028 (Lowest Priority)

Interrupt Masking

Interrupt masking (or disabling) is controlled by the IMASK

that must be set to enable the various interrupt sources. If any

peripheral interrupt (PWMSYNC, PWMTRIP or PIO) is to be

enabled, the IRQ2 interrupt enable bit (Bit 9) of the IMASK

the ADMC328 is shown at the end of the data sheet.

Interrupt Configuration

The IFC and ICNTL registers of the DSP core control and

configure the interrupt controller of the DSP core. The IFC

any of the eight DSP interrupts. Bits 0 to 7 of the IFC register

may be used to clear the DSP interrupts while Bits 8 to 15 can be

used to force a corresponding interrupt. Writing to Bits 11 and

12 in IFC is the only way to create the two software interrupts.

The ICNTL register is used to configure the sensitivity (edge or

level) of the IRQ0, IRQ1 and IRQ2 interrupts and to enable/

disable interrupt nesting. Setting Bit 0 of ICNTL configures the

IRQ0 as edge-sensitive, while clearing the bit configures it for

level-sensitive. Bit 1 is used to configure the IRQ1 interrupt.

Bit 2 is used to configure the IRQ2 interrupt. It is recommended

that the IRQ2 interrupt always be configured as level-sensitive

to ensure that no peripheral interrupts are lost. Setting Bit 4 of

the ICNTL register enables interrupt nesting.

Interrupt Operation

Following a reset, the ROM code on the ADMC328 must copy

a default interrupt vector table into program memory RAM

from address 0x0000 to 0x002F. Since each interrupt source

has a dedicated four-word space in this vector table, it is pos-

sible to code short interrupt service routines (ISRs) in place.

Alternatively, it may be necessary to insert a JUMP instruction

to the appropriate start address of the interrupt service routine if

more memory is required for the ISR.

When an interrupt occurs, the program sequencer ensures that

there is no latency (beyond synchronization delay) when pro-

cessing unmasked interrupts. In the case of the timer, SPORT1,

and software interrupts, the interrupt controller automatically

jumps to the appropriate location in the interrupt vector table.

At this point, a JUMP instruction to the appropriate ISR

is required.

Motor control peripheral interrupts are slightly different. When

a peripheral interrupt is detected, a bit is set in the IRQFLAG

or PIOFLAG1 registers for a PIO interrupt, and the IRQ2 line

is pulled low until all pending interrupts are acknowledged.

The DSP software must determine the source of the interrupts

by reading IRQFLAG register. If more than one interrupt oc-

curs simultaneously, the higher priority interrupt service routine

is executed. Reading the IRQFLAG register clears the PWMTRIP

and PWMSYNC bits and acknowledges the interrupt, thus al-

lowing further interrupts when the ISR exits.

A user’s PIO interrupt service routine must read the PIOFLAG0

and PIOFLAG1 registers to determine which PIO port is the

source of the interrupt. Reading registers PIOFLAG0 and

PIOFLAG1 clears all bits in the registers and acknowledges the

interrupt, thus allowing further interrupts after the ISR exits.

The configuration of all these registers is shown at the end of

the data sheet.

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