ADMC401 datasheet(21/60 Pages) AD

21 / 60 page

ADMC401

–21–

REV. B

The page length is read first and then bytes are loaded from the

top of the page downwards. This causes shorter booting times

for shorter pages. The length of the boot page is given as:

page length = (number of 24-bit PM words/8) – 1

That is, a page length of 0 causes the boot address generator to

generate byte addresses for eight words that reside in 32 sequen-

tial EPROM locations.

A PROM splitter utility (SPL21), part of the Motion Control

Debugger tool set, calculates the proper page length for your

program and orders the bytes of your program according to the

proper protocol. More detailed information about the use of

this PROM splitter utility can be found in the “Booting from

External EPROM with MMAP = BMODE = 0” chapter of the

ADMC401’s Developer’s Reference Manual.

Following a reset, if both MMAP and BMODE are LO, the

boot sequence always boot loads page 0. After reset, boot load-

ing can occur under program control from any one of up to

eight different boot pages. The boot page select field (BPAGE)

in the memory mapped System Control Register specifies which

boot page is to be loaded. To boot from a specific boot page,

first set the BPAGE bits to the desired value and set the boot

force bit (BFORCE) of the System Control Register to initiate a

boot sequence.

The ADMC401 can boot its internal program memory from a

single byte-wide CMOS EPROM such as the 27C64 or the

27C512. A low cost commodity-grade EPROM with an indus-

try-standard access time can be used. The number of wait states

for the boot memory access is selected in the BWAIT field of

the System Control Register. This field can be set to any value

from 0 to 7 to set the number of wait states. The default value

for the BWAIT field is 7 so that seven wait states are inserted

into the reset-initiated boot loading sequence.

Timing of the boot memory access is identical to that of external

program memory or external data memory accesses, except that

the active strobe is

BMS rather than PMS or DMS. To address

eight pages of 8K bytes each, 16 address lines are needed. The

least significant 14 bits are output on the 14-bit address bus

(A13 to A0) while the most significant two bits are output on

the 2 MSBs of the data bus (D23 and D22) during boot memory

accesses. The data is read from the middle eight bits of the data

bus (D15 to D8).

The development tools for the ADMC401 support the creation

of EPROM target files capable of boot loading both internal and

external program and data memory.

External Memory Mode (BMODE = 0, MMAP = 1)

In this mode, with BMODE tied to GND and MMAP tied to

VDD, the ADMC401 is placed in external memory mode and

there is no boot loading. The effect of this mode is that the

internal 2K bank of program memory RAM is relocated from

the bottom of memory (starting at address 0x0000) to the top of

the program memory space (at address 0x3800). In this mode,

program execution starts at external memory address 0x0000, at

which point the first instruction must be placed.

The mode in which BMODE = 1 and MMAP = 0 is not allowed

on the ADMC401 and is an illegal state. The operation of the

ADMC401 is neither guaranteed nor defined with BMODE = 1

and MMAP = 0.

BUS REQUEST/GRANT

The ADMC401 can relinquish control of the external data and

address buses to an external device. The external device requests

the bus by asserting (low) the bus request signal

BR. BR is an

asynchronous input and if the ADMC401 is not performing an

external access, it responds to the active

BR input in the follow-

ing processor cycle by:

•

Three-stating the data and address buses and the

PMS,

DMS, BMS, RD and WR output drivers.

•

Asserting the bus grant

(BG) signal, and

•

Halting program execution (unless Go Mode is enabled).

If Go Mode is enabled, (using the ENA G-MODE instruction)

the ADMC401 continues to execute instructions from its inter-

nal memory. It will not halt program execution until it encoun-

ters an instruction that requires an external access, which includes

an access to any motor control peripheral register. If Go Mode

is not enabled, the ADMC401 always halts before granting the

bus. The processor’s internal state is not affected by granting

the bus, and the serial ports remain active during a bus grant,

whether or not the processor core halts.

If the ADMC401 is performing an external access when the

signal is asserted, it will not grant the buses until the cycle after

the access completes. The entire instruction does not need to be

completed when the bus is granted. If a single instruction re-

quires two external accesses, the bus will be granted between the

two accesses. The second access is performed after

BR is re-

moved. When the

BR input is released, the ADMC401 releases

the

BG signal, re-enables the output drivers and continues pro-

gram execution from the point where it stopped.

BG is always

deasserted in the same cycle that the removal of

BR is recognized.

The bus request feature operates at all times, including when

the ADMC401 is booting and when

RESET is active. During

RESET, BG is asserted in the same cycle that BR is recognized.

During booting, the bus is granted after the completion of load-

ing of the current byte (including any wait states). Using the bus

request during booting is one way to bring the booting operation

under control of a host computer.

The ADMC401 has an additional output, Bus Grant Hang,

BGH, which lets it operate in a multiprocessor system with a

minimum number of wasted cycles. The

BGH pin asserts when

the ADMC401 is ready to execute an instruction but is stopped

because the external bus is granted to another device. The other

device can release the bus by deasserting bus request. Once the

bus is released, the ADMC401 deasserts

BG and BGH and

executes the external access.

POWER-DOWN MODES

The ADMC401 includes a power-down feature that allows the

device to enter a very low power dormant state through hard-

ware or software control. In the power-down mode:

•

Internal clocks are disabled

•

Processor registers and memory contents are maintained

•

Ability to recover from power-down in less than 100tCKI

cycles

•

Interrupt support for housekeeping code before entering

power-down and after recovering from power-down

•

User-selectable power-up context

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