REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

with Regulated Output

ADP3604*

© Analog Devices, Inc., 1996

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700

Fax: 617/326-8703

GENERAL DESCRIPTION

The ADP3604 switched capacitor voltage converter provides a

regulated output voltage with minimum voltage loss and re-

quires a minimum number of external components. In addi-

tion, the ADP3604 does not require the use of an inductor.

The ADP3604 provides up to 120 mA of output current with

±3% output accuracy.

The internal oscillator runs at 240 kHz nominal frequency

which produces an output switching frequency of 120 kHz, al-

lowing the use of small charge pump and filter capacitors.

The ADP3604 is primarily designed for use as a high fre-

quency negative voltage regulator/inverter. The output voltages

of the ADP3604 can range from –1.2 V to –4.0 V, nominally

–3.0 V. For other output voltages, contact the factory.

The ADP3604 dissipates less than 350 mW of power and fea-

tures fast shutdown mode capability (<5 ms) that also drops the

quiescent current to 1.5 mA (typ). For a lower cost, 50 mA out-

put current version, see the ADP3603.

*Patent pending.

FEATURES

Fully Regulated Output

High Output Current: 120 mA

50 mA Version (ADP3603) Is Also Available

Outstanding Precision:

3% Output Accuracy

Input Voltage Range: +4.5 V to +6.0 V

Output Voltage: –3.0 V (Regulated)

High Switching Frequency: 120 kHz (240 kHz Internal

Oscillator)

Shutdown Capability

Small Outline 8-Pin SOIC Package

APPLICATIONS

Voltage Inverters

Voltage Regulators

Computer Peripherals and Add-On Cards

Portable Instruments

Battery Powered Devices

Pagers and Radio Control Receivers

Disk Drives

Mobile Phones

FUNCTIONAL BLOCK DIAGRAM

8

SP D

S1

SN D

S2

S

N

D

B

S3

S

N

D

7

3

1

S4

2

GND

OSC

CLOCK

GEN

4

SD

FEEDBACK

CONTROL

LOOP

5

PIN CONFIGURATION

8-Pin SOIC

(SO-8)

1

2

3

4

8

7

6

5

TOP VIEW

(Not to Scale)

NC = NO CONNECT

ADP3604

NC

GND

SHUTDOWN

ADP3604

8

7

3

C2

1

4

SHUTDOWN

0

OFF

ON

C1

C3

2

5

NOTE

C2: SPRAGUE, 293D105X0010B2W

C1, C3: TOKIN, 1E105ZY5UC205F

Figure 1. Typical Application Circuit