PRELIMINARY

CPC7232

R00J

PRELIMINARY

9

2. Functional Description

The CPC7232 takes a serial stream of input data

along with a synchronous clock signal. As the clock

transits from low to high, the data at the input of each

shift register is shifted through from SR(n) to SR(n+1).

A high data bit, a "1," represents an ON switch; a low

data bit, a "0," represents an OFF switch. Data is input

and shifted through the internal shift register until all

eight shift register positions, SR0 through SR7, are in

the desired state.

CPC7232 to be shifted through the internal shift

register.

CLK: The clock signal's rising edge is associated only

with shifting data into and through the shift register.

CL: The clear line overrides all other inputs. When CL

is high, the shift register is cleared to all 0s and all

latches are set low, which causes all output switches

to be turned OFF immediately. When CL is low, all

output switches remain in whatever state they are in,

ON or OFF, in response to CLK, latch inputs, and the

LE signal.

LE: latch enable controls the state of the latches and

thus the state of the eight switches. If LE is high, then

the latches do not change states, but retain their most

recent status: either ON or OFF. With LE high, input

data and CLK have no effect on the state of the output

switches. If LE is low, then all latch outputs and their

switch states follow the inputs from the shift register.

LE is overridden by CL: no matter what state LE is in,

CL clears the latches. See “Truth Table” on page 10.

eight clock pulses, the first bit of eight input data bits is

SW0 - SW7: The CPC7232 provides eight

high-voltage SPST output switches with a typical

on-resistance of 20

. The two connections of each

switch are not polarity-sensitive.

each switch channel that translate the voltage level of

the latch output signals to an appropriate level for the

voltages being switched.

The high-voltage output switches are turned on and off

in response to the data sent into the latches from the

shift register: data 0 turns a switch OFF, data 1 turns a

switch ON.

Two or more CPC7232 devices can be cascaded to

series. All devices are connected to the same clock

(CLK) signal. LE of all devices would normally be

connected, as would CL, but this is not necessary.

whether it's a single device or several cascaded

devices, ripples through to the last switch output in line

after the application of a full clocking sequence of 8

clock pulses per CPC7232. Setting the serial I/O

device to output the most significant bit (MSB) first,

results in the MSB appearing on SW7 of the last

device in line after a full clocking sequence.

CL

CLK

LE

SW0

SW7

SW0

SW7

SW0

SW7

LE

CL

CLK

LE

CL

CLK

LE

CL

CLK

CPC7232

CPC7232

CPC7232