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CPC7601 数据表(PDF) 6 Page - IXYS Corporation |
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CPC7601 数据表(HTML) 6 Page - IXYS Corporation |
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6 / 11 page ![]() INTEGRATED CIRCUITS DIVISION 6 www.ixysic.com R02 CPC7601 1.5.2 Logic Timing Characteristics (Over recommended operating conditions unless otherwise noted.) 1.5.3 Logic Timing Waveforms Parameter Symbol Test Conditions 0°C +25°C 70°C Units min max min typ max min max Setup Time Before LE Rises tSD - 25 - 25 - - 25 - ns Time Width of LE tWLE VDD=3V 56 -56- -56- VDD=5V 12 -12- -12- Clock Delay Time to Data Out tDO VDD=3V 10 100 10 - 100 10 100 VDD=5V 5 455 - 455 45 Time Width of CL tWCL - 55 - 55 - - 55 - Setup Time, Data to Clock tsu VDD=3V 21 - - 21 - 21 - VDD=5V 7 - -7 -7 - Hold Time, Data from Clock th -2 - 2 - - 2 - Clock Frequency fCLK 50% duty cycle, fDATA= ½ fCLK, VDD=3V -8 - - 8 - 8 MHz 50% duty cycle, fDATA= ½ fCLK, VDD=5V -20- -20-20 Clock Rise and Fall Times tr , tf - - 50 - - 50 - 50 ns Turn-On Time ton VSIG=VPP-10V, RL=10k -5 - - 5 - 5 s Turn-Off Time toff -5 -5 -5 D N-1 D N D N+1 50% 50% 50% 50% D IN LE t WLE t SD 50% 50% CLK t su t h t DO 50% D OUT t off t on 90% 10% OFF ON CL 50% 50% t WCL V OUT |
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