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ADSP-2185

REV. 0

–19–

Parameter

Min

Max

Unit

Bus Request/Grant

Timing Requirements:

tBH

BR Hold after CLKOUT High1

0.25 tCK + 2

tBS

BR Setup before CLKOUT Low

0.25 tCK + 17

Switching Characteristics:

tSD

CLKOUT High to

xMS, RD, WR Disable

0.25 tCK + 10

tSDB

xMS, RD, WR Disable to BG Low

tSE

BG High to xMS, RD, WR Enable

tSEC

xMS, RD, WR Enable to CLKOUT Hig

0.25 tCK – 7

tSDBH

xMS, RD, WR Disable to BGH Low

0ns

tSEH

BGH High to xMS, RD, WR Enable

0ns

NOTES

xMS = PMS, DMS, CMS, IOMS, BMS

1BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on

the following cycle. Refer to the ADSP-2100 Family User’s Manual for

BR/BG cycle relationships.

2BGH is asserted when the bus is granted and the processor requires control of the bus to continue.

CLKOUT

tSD

tSDB

tSE

tSEC

tSDBH

tSEH

tBH

CLKOUT

PMS, DMS

BMS, RD

BGH

tBS

Figure 16. Bus Request–Bus Grant

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