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ADV601LC

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REV. 0

Video Formats — Multiplexed Philips Video

The ADV601LC supports a hybrid mode of operation that is a

cross between standard dual lane Philips and single lane CCIR-

656. In this mode, video data is multiplexed in the same fashion in

CCIR-656, but the values 0 and 255 are not reserved as signaling

values. Instead, external HSYNC and VSYNC pins are used for

signaling and video synchronization. VCLK may range up to

29.5 MHz.

VCLK is driven with up to a 29.5 MHz 50% duty cycle clock

synchronous with the video data. Video data is clocked on the

rising edge of the VCLK signal. The functionality of HSYNC,

VSYNC, and FIELD pins is dependent on three programmable

modes of the ADV601LC: Master-Slave Control, Encode-

Decode Control, and 525-625 Control. Table X summarizes the

functionality of these pins in various modes.

Table X. Philips Multiplexed Video Master and Slave Modes HSYNC, VSYNC, and FIELD Functionality

HSYNC, VSYNC and FIELD

Functionality for Multiplexed

Master Mode (HSYNC, VSYNC

Slave Mode (HSYNC, VSYNC

Philips

and FIELD Are Outputs)

and FIELD Are Inputs)

Encode Mode (video data is input

The ADV601LC completely manages the generation and

These pins are used to control the

to the chip)

timing of these pins. The device driving the ADV601LC

blanking of video and sequencing.

video interface must use these outputs to remain in

sync with the ADV601LC. It is expected that this com-

bination of modes would not be used frequently.

Decode Mode (video data is output

The ADV601LC completely manages the generation

These pins are used to control the

from the chip)

and timing of these pins.

blanking of video and sequencing.

Video Formats—References

For more information on video interface standards, see the

following reference texts.

• For the definition of CCIR-601:

1992 – CCIR Recommendations RBT series Broadcasting Service

(Television) Rec. 601-3 Encoding Parameters of digital television

for studios, page 35, September 15, 1992.

• For the definition of CCIR-656:

1992 – CCIR Recommendations RBT series Broadcasting Service

(Television) Rec. 656-1 Interfaces for digital component video

signals in 525 and 626 line television systems operating at the

4:2:2 level of Rec. 601, page 46, September 15, 1992.

Host Interface

The ADV601LC host interface is a high performance interface

that passes all command and real-time compressed video data

between the host and codec. A 512 position by 32-bit wide,

bidirectional FIFO buffer passes compressed video data to and

from the host. The host interface is capable of burst transfer

rates of up to 132 million bytes per second (4

× 33 MHz). For

host interface pins descriptions, see the Pin Function Descriptions

section. For host interface timing information, see the Host Interface

Timing section.

DRAM Manager

The DRAM Manager provides a sorting and reordering func-

tion on the sub-band coded data between the Wavelet Kernel

and the Programmable Quantizer. The DRAM manager pro-

vides a pipeline delay stage to the ADV601LC. This pipeline

lets the ADV601LC extract current field image statistics (min/

max pixel values, sum of pixel values, and sum of squares) used

in the calculation of Bin Widths and re-order wavelet transform

data. The use of current field statistics in the Bin Width calcu-

lation results in precise control over the compressed bit rate.

The DRAM manager manages the entire operation and refresh of

the DRAM.

The interface between the ADV601LC DRAM manager and

DRAM is designed to be transparent to the user. The ADV601LC

DRAM pins should be connected to the DRAM as called out in

the Pin Function Descriptions section. The ADV601LC re-

quires one 256K word by 16-bit, 60 ns DRAM. The following

is a selected list of manufacturers and part numbers. All parts

can be used with the ADV601LC at all VCLK rates except

where noted. Any DRAM used with the ADV601LC must

meet the minimum specifications outlined for the Hyper Mode

DRAMs listed in Table XI. For DRAM Interface pins descrip-

tions, see the Pin Function Descriptions.

Table XI. ADV601LC Compatible DRAMs

Manufacturer

Part Number

Notes

Toshiba

TC514265DJ/DZ/DFT-60

None

NEC

µPD424210ALE-60

None

NEC

µPD42S4210ALE-60

CBR Self Refresh

feature of this prod-

uct is not needed by

the ADV601LC.

Hitachi

HM514265CJ-60

None

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