ADV7150 datasheet(21/36 Pages) AD

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ADV7150

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REV. A

Palette Select Match Bits Control (MR17–MR16)

These bits allow multiple palette devices to work together.

When bits PS1 and PS0 match MR17 and MR16 respectively,

the device is selected. If these bits do not match, the device is

not selected and the analog video outputs drive 0 mA, see

“Palette Priority Select Inputs” section.

CONTROL REGISTERS

The ADV7150 has 9 control registers. To access each register,

two write operations must be performed. The first write to the

address register specifies which of the 9 registers is to be ac-

cessed. The second access determines the value written to that

particular control register.

Pixel Test Register

(Address Reg (A7–A0) = 00H)

This register is used when the device is in test/diagnostic mode.

It is a 24-bit (8 bits each for RED, GREEN and BLUE) wide

read-only register which allows the MPU to read data on the

pixel port, see “Test Diagnostic” section.

DAC Test Register

(Address Reg (A7–A0) = 01H)

This register is used when the device is in test/diagnostic mode.

It is a 30-bit (10 bits each for RED, GREEN and BLUE) wide

read-only register which allows MPU access to the DAC port,

see “Test Diagnostic” section.

SYNC

, BLANK and IPLL Test Register

(Address Reg (A7–A0) = 02H)

This register is used when the device is in test/diagnostic mode.

It is a 3-bit wide (3 LSBs) read/write register which allows MPU

access to these particular pixel control bits, see “Test Diagnos-

tic” section.

ID Register

(Address Reg (A7–A0) = 03H)

This is an 8-bit wide “Identification” read-only register. For the

ADV7150 it will always return the hexadecimal value 8EH.

Pixel Mask Register

(Address Reg (A7–A0) = 04H)

The contents of the pixel mask register are individually bit-wise

logically AND-ed with the Red, Green and Blue pixel input

stream of data. It is an 8-bit read/write register with D0 corre-

sponding to R0, G0 and B0. For normal operation, this register

is set with FFH.

COMMAND REGISTER 1 (CR1)

(Address Reg (A7–A0) = 05H)

This register contains a number of control bits as shown in the

diagram. CR1 is a 10-bit wide register. However for program-

ming purposes, it may be considered as an 8-bit wide register

(CR18 to CR19 are reserved).

The diagram below shows the various operations under the con-

trol of CR1. This register can be read from as well as written to. In

write mode, “0” should be written to CR11 and CR13 to CR17.

In read mode, CR11 and CR13 to CR19 are returned as zeros.

COMMAND REGISTER 1-BIT DESCRIPTION

Calibration Control (CR10)

This bit automatically calibrates the onboard LOADIN/

LOADOUT synchronization circuit. MR15 of Mode Register

MR1 must be set to “0.”

SYNCOUT

Control (CR12)

This bit specified whether the video SYNCOUT signal is to be

enabled. On power up a “0” is written to the bit and

“SYNCOUT” is set three-state.

*THESE BITS ARE

READ–ONLY

RESERVED BITS.

A READ CYCLE WILL

RETURN ZEROS "00."

CR12

DISABLE

ENABLE

SYNCOUT

SYNCOUT CONTROL

CR17

CR16

CR15

CR14

CR12

CR11

CR10

CR13

RESERVED*

CR11

(0)

THIS BIT SHOULD BE

SET TO ZERO

CALIBRATION CONTROL

CR10

DISABLE

CALIBRATES ON EVERY

VERTICAL SYNC (MR15=0)

CR17-CR13

(00000)

THESE BITS SHOULD

BE SET TO ZERO

CR18

CR19

Command Register 1 (CR1) (CR19–CR10)

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