ADV7150

–6–

REV. A

PIXEL INPUT

DATA*

A

t

PD

A

N

B

N

A

N-1

B

N-1

A

N+1

B

N+1

A

N+2

B

N+2

*INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0–PS1); BLANK; SYNC

CLOCK

LOADOUT

LOADIN

ANALOG

OUTPUT

DATA

t

10

DIGITAL

INPUT

TO ANALOG

OUTPUT

PIPELINE

A

A

IOR, IOR

IOG, IOG

IOB, IOB

IPLL, SYNCOUT

Figure 6. Pixel Input to Analog Output Pipeline with Minimum LOADOUT to LOADIN Delay (2:1 Multiplex Mode)

CLOCK

LOADOUT

PIXEL INPUT

DATA*

LOADIN

ANALOG

OUTPUT

DATA

t

PD

DIGITAL

INPUT

TO ANALOG

OUTPUT

PIPELINE

A

A

A

N

B

N

A

N-1

B

N-1

A

N+1

B

N+1

A

N+2

B

N+2

*INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0–PS1); BLANK; SYNC

τ

τ– t

11

A

IOR, IOR

IOG, IOG

IOB, IOB

IPLL, SYNCOUT

Figure 7. Pixel Input to Analog Output Pipeline with Maximum LOADOUT to LOADIN Delay (2:1 Multiplex Mode)