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ADV7152LS110 数据表(PDF) 23 Page - Analog Devices

部件名 ADV7152LS110
功能描述  CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC
PDF  32 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADV7152LS110 数据表(HTML) 23 Page - Analog Devices

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ADV7152
–23–
REV. B
Variations on RS-343A
Various other video output configurations can be implemented
by the ADV7152, including RS-170. Values of RSET for particu-
lar output video formats/levels are calculated by using the equa-
tions for RSET given in the “Pin Configuration” section. The
table shows calculated values of RSET for some of the most com-
mon variants on the RS-343A standard. The associated wave-
forms are shown in the diagrams.
RSET ( )
Video Signal
265
SYNC
decoded on IOG; Pedestal = 0 IRE
280
No SYNC decoded; Pedestal = 7.5 IRE
259
No SYNC decoded; Pedestal = 0 IRE
WHITE
LEVEL
IOR, IOB
IOG
mA
mA
V
V
26.67 1.000
0.698
18.62
00
00
8.05
0.302
BLACK/BLANK
LEVEL
SYNC
LEVEL
100 IRE
43 IRE
Figure 29. Composite Video Waveform (SYNC
Decoded on IOG; Pedestal = 0 IRE; RSET = 265 Ω)
WHITE LEVEL
BLACK LEVEL
IOR, IOB, IOG
mA
V
19.05
0.714
00
1.44
0.054
BLANK LEVEL
92.5 IRE
7.5 IRE
Figure 30. Composite Video Waveform
(Pedestal = 7.5 IRE; RSET = 280 Ω)
WHITE LEVEL
IOR, IOB, IOG
mA
V
19.05
0.714
00
BLACK/ BLANK
LEVEL
100 IRE
Figure 31. Composite Video Waveform
(Pedestal = 0 IRE; RSET = 259 Ω)
IPLL Synchronization Output Control
This output synchronization signal is used in applications where
it is necessary to synchronize multiple palette devices (ADV7150
+ ADV7151) to subpixel resolution. Each devices IPLL output
signal is in phase with its analog RGB output signal. If multiple
devices have differing output delays, the time difference can be
derived from the IPLL signals. This time difference is then used
to phase shift the CLOCK inputs on one or other of the devices
inputs.
The IPLL signal is internally triggered by either the falling edge
of SYNC or BLANK as determined by CR21 of Command
Register 2.



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