ADV7175 datasheet(21/36 Pages) AD

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ADV7175/ADV7176

REV. A

–21–

MR21

MR27

MR22

MR23

MR26

MR25

MR24

MR20

CHROMINANCE

CONTROL

ENABLE COLOR

DISABLE COLOR

MR24

GENLOCK SELECTION

DISABLE GENLOCK

ENABLE SUBCARRIER

RESET PIN

ENABLE RTC PIN

MR22 MR21

RGB/YUV

CONTROL

RGB OUTPUT

YUV OUTPUT

MR26

SQUARE PIXEL

CONTROL

DISABLE

ENABLE

MR20

BURST

CONTROL

ENABLE BURST

DISABLE BURST

MR25

LOWER POWER

MODE

DISABLE

ENABLE

MR27

CCIR624/CCIR601

CONTROL

CCIR624 OUTPUT

CCIR601 OUTPUT

MR23

Figure 38. Mode Register 2

MR31

MR37

MR32

MR33

MR36

MR35

MR34

MR30

DAC OUTPUT

SWITCHING

MR37

DAC A

COMPOSITE

GREEN/LUMA/Y

DAC B

BLUE/COMP/U

DAC C

RED/CHROMA/V

DAC D

GREEN/LUMA/Y

COMPOSITE

MR36-MR30

(RESERVED)

ZERO SHOULD BE

WRITTEN TO THESE BITS

Figure 40. Mode Register 3

CCIR624/CCIR601 Control (MR23)

This bit switches the video output between CCIR624 and

CCIR601 video standard.

Chrominance Control (MR24)

This bit enables the color information to be switched on and off

the video output.

Burst Control (MR25)

This bit enables the burst information to be switched on and off

the video output.

RGB/YUV Control (MR26)

This bit enables the output from the RGB DACs to be set to

YUV output video standard. Bit MR06 of Mode Register 0

must be set to Logic Level “1” before MR26 is set.

Lower Power Control (MR27)

This bit enables the lower power mode of the ADV7175/

ADV7176.

NTSC PEDESTAL CONTROL REGISTERS 3–0

(PCE15–0, PCO15–0)

(Subaddress (SR4–SR0) = 11-0EH)

These 8-bit wide registers are used to set up the NTSC pedestal

on a line by line basis in the vertical blanking interval for both

odd and even fields. Figure 39 shows the four control registers.

A Logic “1” in any of the bits of these registers has the effect of

turning the pedestal off on the equivalent line.

FIELD 1/3

PCO6

PCO5

PCO3

PCO1

PCO4

PCO2

PCO0

PCO7

LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10

PCO14

PCO13

PCO11

PCO9

PCO12

PCO10

PCO8

PCO15

LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18

FIELD 1/3

FIELD 2/4

PCE6

PCE5

PCE3

PCE1

PCE4

PCE2

PCE0

PCE7

LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10

PCE14

PCE13

PCE11

PCE9

PCE12

PCE10

PCE8

PCE15

LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18

FIELD 2/4

Figure 39. Pedestal Control Registers

MODE REGISTER 3 MR3 (MR37–30)

(Address (SR4–SR0) = 12H)

Mode Register 3 is an 8-bit wide register.

Figure 34 shows the various operations under the control of

Mode Register 3. Bits MR36–MR30 are reserved and Logic “0”

should be written to them.

MODE REGISTER 3 (MR37–MR30) DESCRIPTION

DAC Switching Control (MR37)

This bit is used to switch the luminance signal onto the compos-

ite DAC. Figure 40 illustrates the DAC outputs and how they

switch when MR 37 is set to Logic “1”.

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