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ADV7192 数据表(PDF) 21 Page - Analog Devices

部件名 ADV7192
功能描述  Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs
PDF  69 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADV7192 数据表(HTML) 21 Page - Analog Devices

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ADV7192
–21–
REV. 0
XXXXXXX
XXXXXXX
XXXXXXX
XXXXXXX
XXXXXXX
XXXXXXX
XXXXXXX
OFF
0
DIGITAL TIMING SIGNALS SUPPRESSED
TIMING ACTIVE
1
VALID VIDEO
VALID VIDEO
VALID VIDEO
BLACK VALUE
BLACK VALUE WITH SYNC
RESET
DAC D,
DAC E
DAC F
DAC A,
DAC B,
DAC C
MR26
PIXEL_DATA_VALID
DIGITAL TIMING
Figure 37.
RESET Sequence Timing Diagram
COMPOSITE
VIDEO
e.g., VCR
OR CABLE
M
U
X
HSYNC
VSYNC
CLOCK
GREEN/COMPOSITE/Y
BLUE/LUMA/U
ADV7192
P7–P0
SCRESET/RTC/TR
MPEG
DECODER
VIDEO
DECODER
ADV7185
LCC1
P19–P12
RED/CHROMA/V
GREEN/COMPOSITE/Y
BLUE/LUMA/U
RED/CHROMA/V
H/L TRANSITION
COUNT START
LOW
128
RTC
TIME SLOT: 01
14
67 68
NOT USED IN
ADV7192
19
VALID
SAMPLE
INVALID
SAMPLE
FSCPLL INCREMENT
1
8/LINE
LOCKED CLOCK
5 BITS
RESERVED
SEQUENCE
BIT2
RESET
BIT3
RESERVED
4 BITS
RESERVED
21
0
13
14 BITS
RESERVED
0
NOTES:
1FSC PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7192 FSC DDS REGISTER IS FSC PLL INCREMENTS
BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE
SUBCARRIER FREQUENCY REGISTERS OF THE ADV7192.
2SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
3RESET BIT
RESET ADV7192’s DDS
GLL
Figure 38. RTC Timing and Connections



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