VDD or

VDDIO

POR

(Internal)

VIO

LM8335

SNVS840 – JUNE 2012

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Figure 7. Internal VDD or VDDIO POR Timing

Register Information

Table 1. Register Listing

Register Name

Addr

Bit

Default

Description

Software reset register

CNTL_REG

0x00

7:0

0x00

Bit 0 = 0, no effect

Bit 0 = 1, reset registers to default values (self-clearing)

GPO pin pull resistor direction

0 = pull-down

1 = pull-up

GPO_PULL_DIR

0x01

7:0

0x00

Note: When CFG = GND, writing to this register has no effect.

The pull-down resistor will be disabled after the first write to

the GPO_OUT_DATA register.

GPO pin internal pull resistor enable

0 = disabled

1 = enabled

GPO_PULL_ENABLE

0x02

0xFF

0xFF

Note: GPO_PULL_DIR register selects if the resistor is a pull-

up or a pull-down. When CFG = GND, writing to this register

has no effect. The pull-down resistor will be disabled after the

first write to the GPO_OUT_DATA register.

GPO output high state (full buffer or high-z).

0 = full buffer

1 = high-z (open-drain behavior)

GPO_OUT_HIGH_CFG

0x03

7:0

0xFF

Note: When CFG = GND, writing to this register has no effect.

The pull-down resistor will be disabled, and all GPO outputs

will be in the actively driven state (not high-z) after the first

write to the GPO_OUT_DATA register.

10

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