FUNCTIONAL BLOCK DIAGRAM

REG

A

SHIFT

REGISTER

DECODE

VOUTA

VOUTB

VOUTC

VOUTD

2

3

6

7

8

15

16

9

GND

CLSEL

4

VREFLO

VSS

5

VREFHI

VDD

10

12

11

13

14

SDI

CLK

NC

CS

LD

REG

A

1

DAC A

REG

B

DAC B

REG

C

DAC C

REG

D

DAC D

CLR

12

4

2

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

a

Quad 12-Bit Serial

Voltage Output DAC

DAC8420

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700

Fax: 617/326-8703

FEATURES

Guaranteed Monotonic Over Temperature

Excellent Matching Between DACs

Unipolar or Bipolar Operation

Buffered Voltage Outputs

High Speed Serial Digital Interface

Reset to Zero- or Center-Scale

Wide Supply Range, +5 V-Only to

15 V

Low Power Consumption (35 mW max)

Available in 16-Pin DIP and SOL Packages

APPLICATIONS

Software Controlled Calibration

Servo Controls

Process Control and Automation

ATE

The DAC8420 is available in 16-pin epoxy DIP, cerdip, and

wide-body SOL (small-outline surface mount) packages. Opera-

tion is specified with supplies ranging from +5 V-only to

±15 V,

with references of +2.5 V to

±10 V respectively. Power dissipa-

tion when operating from

±15 V supplies is less than 255 mW

(max), and only 35 mW (max) with a +5 V supply.

For applications requiring product meeting MIL-STD-883,

contact your local sales office for the DAC8420/883 data sheet,

which specifies operation over the –55

°C to +125°C tempera-

ture range.

GENERAL DESCRIPTION

The DAC8420 is a quad, 12-bit voltage-output DAC with serial

digital interface, in a 16-pin package. Utilizing BiCMOS tech-

nology, this monolithic device features unusually high circuit

density and low power consumption. The simple, easy-to-use

serial digital input and fully buffered analog voltage outputs

require no external components to achieve specified performance.

The three-wire serial digital input is easily interfaced to micro-

processors running at 10 MHz rates, with minimal additional

circuitry. Each DAC is addressed individually by a 16-bit serial

word consisting of a 12-bit data word and an address header.

The user-programmable reset control CLR forces all four DAC

outputs to either zero or midscale, asynchronously overriding

the current DAC register values. The output voltage range, de-

termined by the inputs VREFHI and VREFLO, is set by the

user for positive or negative unipolar or bipolar signal swings

within the supplies allowing considerable design flexibility.