DAC8562FS datasheet(2/16 Pages) AD

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DAC8562–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Parameter

Symbol

Condition

Min

Typ

Max

Units

STATIC PERFORMANCE

Resolution

Note 2

Bits

Relative Accuracy

INL

E Grade

–1/2

±1/4

+1/2

LSB

F Grade

–1

±3/4

LSB

Differential Nonlinearity

DNL

No Missing Codes

–1

±3/4

LSB

Zero-Scale Error

VZSE

Data = 000H

+1/2

LSB

Full-Scale Voltage

VFS

Data - FFFH

E Grade

4.087

4.095

4.103

F Grade

4.079

4.095

4.111

Full-Scale Tempco

TCVFS

Notes 3, 4

±16

ppm/

°C

ANALOG OUTPUT

Output Current

IOUT

Data = 800H

±5

±7mA

Load Regulation at Half Scale

LDREG

RL = 402

Ω to ∞, Data = 800

LSB

Capacitive Load

No Oscillation4

500

REFERENCE OUTPUT

Output Voltage

VREF

2.484

2.500

2.516

Output Source Current

IREF

Note 5

Line Rejection

LNREJ

0.08

%/V

Load Regulation

LDREG

IREF = 0 to 5 mA

0.1

%/mA

LOGIC INPUTS

Logic Input Low Voltage

VIL

0.8

Logic Input High Voltage

VIH

2.4

Input Leakage Current

IIL

µA

Input Capacitance

CIL

Note 4

INTERFACE TIMING SPECIFICATIONS1, 4

Chip Enable Pulse Width

tCEW

Data Setup

tDS

Data Hold

tDH

Clear Pulse Width

tCLRW

AC CHARACTERISTICS4

Voltage Output Settling Time

±1 LSB of Final Value

µs

Digital Feedthrough

nV sec

SUPPLY CHARACTERISTICS

Positive Supply Current

IDD

VIH = 2.4 V, VIL = 0.8 V

VIL = 0 V, VDD = +5 V

0.6

Power Dissipation

PDISS

VIH = 2.4 V, VIL = 0.8 V

VIL = 0 V, VDD = +5V

Power Supply Sensitivity

PSS

∆V

DD = ± 5%

0.002

0.004

%/%

NOTES

1All input control signals are specified with t

r = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.

21 LSB = 1 mV for 0 to +4.095 V output range.

3Includes internal voltage reference error.

4These parameters are guaranteed by design and not subject to production testing.

5Very little sink current is available at the REFOUT pin. Use external buffer if setting up a virtual ground.

6The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in

this 6 LSB region.

Specifications subject to change without notice.

–2–

(@ VDD = +5.0

5%, RS = No Load, –40 C

≤ T

≤ +85 C, unless otherwise noted)

REV. A

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