SMP18

REV. C

–6–

14

13

12

11

16

15

10

9

8

1

2

3

4

7

6

5

SMP18

R3

2k

Ω

R4

1k

Ω

R1

10

Ω

D1

C1

10µF

C2

1µF

+

+15V

R2

10k

Ω

R2

10k

Ω

R2

10k

Ω

R2

10k

Ω

R2

10k

Ω

R2

10k

Ω

R2

10k

Ω

R2

10k

Ω

Burn-in Circuit

APPLICATIONS INFORMATION

The SMP18, a multiplexed octal S/H, minimizes board space

in systems requiring cycled calibration or an array of control

voltages. When used in conjunction with a low cost 16-bit D/A,

the SMP18 can easily be integrated into microprocessor based

systems. Since the SMP18 features break-before-make switching

and an internal decoder, no external logic is required. The

SMP18 has an internally regulated TTL supply so that

TTL/CMOS compatibility is maintained over the full supply

range. See Figure 1 for channel decode address information.

POWER SUPPLIES

The SMP18 is capable of operating with either single or dual

supplies over a voltage range of 7 to 15 volts. Based on the sup-

range, which is:

Note that several specifications, including acquisition time, off-

set and output voltage compliance, will degrade for supply volt-

ages of less than 7 V.

If split supplies are used, the negative supply should be bypassed

with a 0.1

µF capacitor in parallel with a 10 µF to ground. The

internal hold capacitors are connected to this supply pin, and

any noise will appear at the outputs.

In single supply applications, it is extremely important that the

ground noise or disturbance will directly couple to the output of

the sample-and-hold degrading the signal-to-noise performance.

The analog and digital ground traces on the circuit board should

be physically separated to reduce digital switching noise from

entering the analog circuitry.

POWER SUPPLY SEQUENCING

nals. The SMP18 has been designed to be immune to latchup,

but standard precautions should still be taken.

OUTPUT BUFFERS (Pins 1, 2, 4, 5, 12, 13, 14, 15)

The buffer offset specification is 10 mV; this is less than 1/2

LSB of an 8-bit DAC with 10 V full scale. The hold step (mag-

nitude of step caused in the output voltage when switching from

sample-to-hold mode, also referred to as the pedestal error or

sample-to-hold offset) is about 4 mV with little variation over

the full output voltage range. The droop rate of a held channel

is 2 mV/s typical and 40 mV/s maximum.

The buffers are designed to drive loads connected to ground.

The outputs can source more than 20 mA over the full voltage

split supply operation, symmetrical output swings can be ob-

tained by restricting the output range to 2 V from either supply.

On-chip SMP18 buffers eliminate potential stability problems

associated with external buffers; outputs are stable with capaci-

tive loads up to 500 pF. However, since the SMP18’s buffer

outputs are not short circuit protected, care should be taken to

avoid shorting any output to the supplies or ground.

SIGNAL INPUT (Pin 3)

The signal input should be driven from a low impedance voltage

source such as the output of an op amp. The op amp should

have a high slew rate and fast settling time if the SMP18’s ac-

quisition time characteristics are to be maintained. As with all

CMOS devices, all input voltages should be kept within range of

≤ V

IN

≤ V

latchup. If single supply operation is desired, op amps such as

the OP183 or AD820 that have input and output voltage com-

pliances including ground, can be used to drive the inputs. Split

supplies, such as

±7.5 V, can be used with the SMP18.