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SSM2005 数据表(PDF) 13 Page - Analog Devices

部件名 SSM2005
功能描述  Decoder 5.1-Channel Soundfield Generator
PDF  15 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

SSM2005 数据表(HTML) 13 Page - Analog Devices

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SSM2005
–13–
REV. 0
APPLICATION NOTES
Figure 8 shows a typical SSM2005 application schematic. The
stereo source signal is connected to the SSM2005 audio signal
inputs at Pins 7 and 10, as well as the Left/Right level detectors
at Pins 19, 20, 22, and 23. The input signal goes through the
autobalance circuitry and can be accessed at Pins 6 and 9.
A sum (L+R) and difference (L–R) signal is available at Pins 15
and 16, respectively. These signals are fed into the Front/Rear
level detector at Pins 27 and 28.
The L+R signal is also fed internally to the center channel VCA
to produce the center channel output at Pin 48. In addition, the
L–R signal is fed into two external filters, creating a low-band and
high-band signal with a crossover frequency of 2 kHz. The cross-
over filters are both 3
rd order Bessel filters, providing a minimum
group delay to the surround channels. The L–R high-band signal
is connected to Pin 17, and the L–R low-band signal is connected
to Pin 18. These two pins provide the multiband steering to the
two surround outputs.
Low-pass filters are inserted between Pins 1 and 2, and Pins 3
and 4. These filters are used for the center-canceling circuitry,
which removes center channel information from the left front
and right front outputs. This circuitry is only active in Video
mode, providing maximum channel separation between the
center and front outputs. In an application that will only use
Music mode, these active filters can be removed and replaced
with a 1
µF capacitor between Pins 1 and 2, and Pins 3 and 4.
The capacitors and resistors connected to Pins 21, 24, 25, 26, 29,
30, 31 and 32 are used to create the time constants for the steer-
ing circuitry. The values shown in Figure 8 are strongly recom-
mended. Variation from these values will result in improper
operation of the Circle Surround decoder, and may result in the
assembled unit failing SRS Labs approval.
The noise generator output is at Pin 42, and the input to the noise
steering circuit is at Pin 43. The R-C network connected between
Pins 42 and 43 is used to remove dc voltage and high frequencies,
which could damage speakers. Other noise-shaping circuitry could
be used here to create noise patterns other than white, or to further
attenuate the noise output with a resistor divider.
Adding a Subwoofer Output
The SSM2005 provides an output of the summed Left In and
Right In signals. This L+R signal is used to drive the center chan-
nel output, and it can also be used to provide a subwoofer chan-
nel by connecting the output from Pin 15 to a low-pass filter. The
schematic for such a configuration is shown in Figure 9.
Here, Pin 15 is connected to a 2nd order Bessel low-pass filter.
The circuit uses the SSM2275, a low noise audio op amp that
can run from the same
±6 V that power the SSM2005. Using
the component values shown in Figure 9, the filter’s cutoff
frequency is 100 Hz.
48
47
46
45
44
7
10
39
SSM2005*
LEFT IN
RIGHT IN
10 F
10 F
CENTER
LF
RF
LS
RS
OUTPUTS
*ADDITIONAL PINS
OMITTED FOR CLARITY
SSM2275
2.05k
4.23k
1 F
SUBWOOFER
0.47 F
fC = 100Hz
Figure 9. Adding a Subwoofer Output
Implementing a Stereo Bypass Mode
Figure 10 shows a schematic for implementing a clickless stereo
bypass around the SSM2005. The stereo bypass mode allows
the user to defeat the Circle Surround decoding and listen to
two-channel stereo from the left front and right front speakers.
The SSM2402 is a clickless dual audio single-pole single-throw
(SPST) switch. When the control voltage, VBYP, is low (below
+0.8 V) the switch is open, and the five channel outputs are
connected to the outputs of the SSM2005. When VBYP goes
high (above +2.0 V) the SSM2402 switch closes, connecting the
LF and RF outputs to Left In and Right In respectively. At the
same time, a data byte should be loaded into the SSM2005,
placing the Circle Surround decoder into Mute Mode. The data
byte required for Mute Mode can be found in Table III, and the
logic timing diagrams can be found in Figure 7.
48
47
46
45
44
7
10
39
14
13
12
11
10
9
8
1
2
3
4
5
6
7
SSM2402
+6V
6V
VBYP
VBYP HIGH =
STEREO MODE
VBYP LOW = CIRCLE
SURROUND MODE
SSM2005*
DATA IN
LEFT IN
RIGHT IN
10 F
10 F
CENTER
LF
RF
LS
RS
OUTPUTS
*ADDITIONAL PINS
OMITTED FOR CLARITY
x DENOTES A DON'T CARE BIT
VBYP LOW = CS MODE
0 0 0 x x x xx
Figure 10. Implementing a Clickless Stereo Bypass Mode



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