SSM2160/SSM2161

–3–

REV. 0

Timing Characteristics

Timing

Symbol

Description

Min

Typ

Max

Units

Input Clock Pulse Width, Low

200

ns

Input Clock Pulse Width, High

200

ns

Data Setup Time

50

ns

Data Hold Time

75

ns

Positive CLK Edge to End of Write

100

ns

Write to Clock Setup Time

50

ns

End of Load Pulse to Next Write

50

ns

End of Write to Start of Load

50

ns

Load Pulse Width

250

ns

Load Pulse Width (3-Wire Mode)

250

ns

NOTES

1. An idle HI (CLK-HI) or idle LO (CLK-LO) clock may be used. Data is latched on the negative edge.

2. For SPI or microwire three-wire bus operation, tie LD to WRITE, and use WRITE pulse to drive both pins. (This generates an automatic internal load signal.)

4. The first data byte selects an address (MSB HI), and subsequent MSB LO states set gain/attenuation levels. Refer to the Address/Data Decoding Truth Table.

5. Data must be sent MSB first.

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

1

1

1

1

CLK

DATA

WRITE

LD

t

WL

t

L

t

LW

t

DS

t

CH

0

0

1

1

0

1

1

0

CLK

DATA

WRITE

LD

t

CL

D7

t

WC

t

CW

MSB

Figure 1. Timing Diagrams