Features

eroflex Circuit Technology – RISC TurboEngines For The Future © SCD5230 REV 1 12/22/98

Block Diagram

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Full militarized QED RM5230 microprocessor

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Dual Issue superscalar microprocessor - can issue one

integer and one floating-point instruction per cycle

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100, 133 and 150 MHz operating frequency – Consult

Factory for latest speeds

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228 Dhrystone2.1 MIPS

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SPECInt95 4.2 SPECfp95 4.5

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System interface optomized for embedded

applications

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32-bit system interface lowers total system cost with up to

87.5 MHz operating frequency

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High performance write protocols maximize uncached

write bandwidth

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Operates at processor clock divisors 2 through 8

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5V tolerant I/O's

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IEEE 1149.1 JTAG boundary scan

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Integrated on-chip caches

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16KB instruction - 2 way set associative

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16KB data - 2 way set associative

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Virtually indexed, physically tagged

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Write-back and write-through on per page basis

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Early restart on data cache misses

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Integrated memory management unit

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Fully associative joint TLB (shared by I and D translations)

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48 dual entries map 96 pages

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Variable page size (4KB to 16MB in 4x increments)

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High-performance floating point unit

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Single cycle repeat rate for common single precision

operations and some double precision operations

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Two cycle repeat rate for double precision multiply and

double precision combined multiply-add operations

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Single cycle repeat rate for single precision combined

multiply-add operation

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MIPS IV instruction set

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Floating point multiply-add instruction increases

performance in signal processing and graphics

applications

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Conditional moves to reduce branch frequency

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Index address modes (register + register)

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Embedded application enhancements

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Specialized DSP integer Multiply-Accumulate instruction

and 3 operand multiply instruction

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I and D cache locking by set

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Optional dedicated exception vector for interrupts

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Fully static CMOS design with power down logic

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Standby reduced power mode with WAIT instruction

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2.5 Watts typical with less than 70 mA standby current

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package configuration

Preliminary

Store Buffer

Data Set A

Data Tag A

DTLB Physical

Data Tag B

Instruction Set A

Integer Instruction Register

FP Instruction Register

Instruction Set B

Address Buffer

Instruction Tag A

ITLB Physical

Instruction Tag B

Sys AD

Write Buffer

Read Buffer

Data Set B

DBus

Control

Floating-point

Register File

Joint TLB

Tag

Aux Tag

IntIBus

Floating-point

Coprocessor 0

Unpacker/Packer

MAdd, Add, Sub,Cvt

PC Incrementer

Branch Adder

DVA

Load Aligner

Integer Register File

Integer/Address Adder

Data TLB Virtual

Shifter/Store Aligner

Logic Unit

Integer Multiply, Divide

Instruction TLB Virtual

Phase Lock Loop

Instruction Select

FPIBus

ABus

System/Memory

Control

Program Counter

IVA

Div, SqRt

32-Bit Superscaler Microprocessor

ACT5230