ACT7005 datasheet(10/29 Pages) AEROFLEX

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Aeroflex Circuit Technology

SCD7005 REV B 8/2/01

Plainview NY (516) 694-6700

Remote Terminal Command Word Register: This

It contains all valid received command words, i.e.

transmit, receive, and mode command.

Receive Command Word Register: After the

reception of a valid receive message, and the

GOOD BLOCK interrupt has been issued, the

Receive Command word will be transferred from the

Remote Terminal Command Word Register to this

command words is to maximize the time a

subsystem has to read this command since GOOD

BLOCK comes at the end of the data transfer, and

the next command word could overwrite the contents

of the Remote Terminal Command Word Register.

This is a READ ONLY register in RT mode.

Command Word #1 Register: This register

contains the first command word to be transmitted

during an RT to RT transfer, or the command word

for a BC to RT, or RT to BC transfer. This register is a

read or write register.

Vector Word/Command Word #2 Associated

Mode Data Register: This register is used to

accomplish multiple functions in Bus Controller and

Remote Terminal Modes. In BC Mode it will contain

the second command word for (RT to RT) transfers,

or Associated Mode Data that is required by certain

mode codes; i.e., Sync (with data). When operated

in the RT Mode, this register contains the Vector

Word required by mode code Transmit Vector Word

Command.

STATUS Word #1 Register: The utilization of this

returned status word for BC to RT, RT to BC mode,

or the first returned status in RT to RT mode. At

reset or the initiation of a bus transfer, the contents

of this register will be set to all high, FFFFH.

Synchronize/Status Word #2/ Return Mode Data

either contain the second returned status word for

RT to RT transfers or the returned mode data; i.e.,

BIT word or Vector word, Last Status word, or Last

Command word. In BC mode this register is

initialized to all highs, FFFFH. Unlike the other status

word register, this does function in the RT mode, but

is still read only in either mode. In RT mode it will

contain the SYNC data word received in association

with the Synchronize with Data Mode Code.

Operation Register: This register contains

information provided by the subsystem to control the

interface. This register sets up the mode of operation

for the interface (BC or RT), selects the available

options (BUS Select and Auto Retry), and contains

information for reading or writing data to the Internal

RAM. (See note below.) This register also provides

software control of the DBCACC, SERVREQ, and

SSERR bits of the status word. Following power-up

master reset, bit 7 of this register will be set high.

This bit corresponds to the busy bit of the Remote

Terminal Status Word. The subsystem reads and

writes to this register under l/O commands. The

transfer functions defined by this register are

executed by either of the two l/O EXECUTE

Commands.

Not

e: The Internal RAM is divided into transmit or

receive sections. In general, data is written to the transmit

section and read from the receive section. However,

either section may be read from or written to via the T/R

bit in this register.

SELF TEST

The inclusion of simple wraparound self test

circuitry in the protocol section insures that a high

percentage of coverage is attainable. Testing

requires simple subsystem intervention. A word is

first placed in the VECTOR WORD Register. Test bit

9 in the OPERATION Register is asserted low and

the l/O TEST TRIGGER address is written. The LT

LOCAL (Bit 10 of the Operation Register)

determines if this will be an ON/OFF line test. OFF

line tests are performed by the inclusion of digital

multiplexers in front of the encoder, bypassing the

transceiver, providing a path to the decoder. The ON

line tests are accomplished when not connected to a

bus network, such as a maintenance test station,

since this test utilizes the transceiver to provide the

loop back path instead of the internal multiplexers. In

this mode test words would appear on the bus. First,

the primary bus will be tested with the data that

resides in the VECTOR WORD Register. It is

encoded then looped back, decoded and presented

to the subsystem as a normal data transfer would be

accomplished. This word will be stored in the RT

Command Word Register. The secondary bus is

sequentially tested after the primary bus is

completed, utilizing the word residing in the

VECTOR WORD Register. Upon successful

completion of the test, the PASS interrupt will be

asserted low.

In addition to this test of the protocol section, the

subsystem data handling capability is also testable

via the OPERATION Register. This is accomplished

by writing a message to the INPUT FIFO Buffer; this

data can be placed in any location determined by the

SA0 through SA4 Bits, or in either the transmit or

receive section (T/R Bit). This same data can now

be transferred from this RAM location to the

OUTPUT FIFO Buffer and compared with the data

originally written to the INPUT FIFO Buffer.

Providing this type of testing provides a high degree

of functional verification.

This test implementation not only verifies

MIL-STD-1553 protocol compliance (proper sync

character, 16 data bits, Manchester 11 coding, odd

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