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ZPM3570 Data Sheet - 05/25/11

2.5 Module Pin Out

Pin

Name

I/O

Description

1

GND

-

Ground

2

Reserved

O

Internal serial flash on/off control (active low),for debugging use only

3

PC4/JTMS

I/O

Programmable I/O control available to the host, or JTAG mode select

4

PB0/IRQA

I/O

Programmable I/O control available to the host, or an interrupt input

5

Reserved

O

Internal serial flash nCS, for debugging use only

6

PB6/ADC1/IRQB

I/O

Programmable I/O control available to the host, or ADC input, or an

interrupt input

7

PC1/ADC3

I/O

Programmable I/O control available to the host, or an ADC input

8

SWCLK/JTCK

I

JTAG/Serial Wire debugging port clock

9

PC0/JRST/IRQD

I/O

Programmable I/O control available to the host, or an interrupt input, or

the JTAG reset input

10

GND

-

Ground

11

PB5/ADC0

I/O

Programmable I/O control available to the host, or an ADC input

12

GND

-

Ground

13

GND

-

Ground

14

GND

-

Ground

15

GND

-

Ground

16

Reserved

I/O

Not connected in ZPM3750

17

GND

-

Ground

18

Reserved

O

Used internally as the LNA on (active low), for debugging use only

19

nRESET

I

Module reset signal (Internal pull-up)

20

GND

-

Ground

21

GND

-

Ground

22

PA3

I/O

Programmable I/O control available to the host

23

GND

-

Ground

24

PC6/OSC32B

I/O

Programmable I/O control available to the host, or 32.768 kHz crystal

25

PC7/OSC32A

I/O

Programmable I/O control available to the host, or 32.768 kHz crystal

26

SC1SCLK/PB3

I/O

SPI port 1 clock, or programmable I/O control available to the host

27

Reserved

O

Used internally as the serial flash MOSI, for debugging use only

28

Reserved

O

Used internally as the serial flash MISO, for debugging use only

29

VBATT

PI

Module power supply

30

Reserved

O

Used internally as the serial flash clock, for debugging use only

31

PA4/ADC4

I/O

Programmable I/O control available to the host, or ADC input

32

GND

-

Ground

33

PA5/ADC5/nBOOTMODE

I/O

Programmable I/O control available to the host, or ADC input, or Boot

control, must be left open or pulled high during the reset to enable the

normal firmware boot process.

34

SC1MISO(s)

/SC1MOSI(m)/TXD/PB1/SC1SDA

I/O

SPI port 1 MISO (slave)/ MOSI (master) signal, UART TXD signal, I2C

port 1 DATA signal, or programmable I/O control available to the host

35

SC1MOSI(s)

/SC1MISO(m)/RXD/PB2/SC1SCL

I/O

SPI port 1 MOSI (slave)/ MISO (master) signal, UART RXD signal, I2C

port 1 CLK signal, or programmable I/O control available to the host.

36

PC2/JTDO/SWO

I/O

Programmable I/O control available to the host, or Serial Wire port OUT-

PUT signal, or JTAG data out

37

SC1nSSEL/PB4

I/O

SPI port 1 slave select, or programmable I/O control available to the host

38

PC3/JTDI

I/O

Programmable I/O control available to the host, or JTAG data in

39

GND

-

Ground

40

GND

-

Ground

41

GND

-

Ground