AD9508PCBZ datasheet(29/40 Pages) AD

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Data Sheet

AD9508

Rev. A | Page 29 of 40

Table 20. Serial Control Port Timing

Parameter

Description

tDS

Setup time between data and the rising edge of SCLK

tDH

Hold time between data and the rising edge of SCLK

tCLK

Period of the clock

Setup time between the

CSE

falling edge and the SCLK rising edge (start of the communication cycle)

Setup time between the SCLK rising edge and

CSE

rising edge (end of the communication cycle)

tHIGH

Minimum period that SCLK should be in a logic high state

tLOW

Minimum period that SCLK should be in a logic low state

tDV

SCLK to valid SDIO and SDO (see Figure 51)

I2C SERIAL PORT OPERATION

The I2C interface has the advantage of requiring only two control

pins and is a de facto standard throughout the I2C industry.

However, its disadvantage is the programming speed, which is

400 kbps maximum. The AD9508 I2C port design is based on

the I2C fast mode standard; therefore, it supports both the 100 kHz

standard mode and 400 kHz fast mode. Fast mode imposes a glitch

tolerance requirement on the control signals; that is, the input

receivers ignore pulses of less than 50 ns duration.

The AD9508 I2C port consists of a serial data line (SDA) and

a serial clock line (SCL). In an I2C bus system, the AD9508 is

connected to the serial bus (data bus SDA and clock bus SCL)

as a slave device; that is, no clock is generated by the AD9508.

The AD9508 uses direct 16-bit memory addressing rather than

traditional 8-bit memory addressing.

The AD9508 allows up to four unique slave devices to occupy

the I2C bus. These slave devices are accessed via a 7-bit slave

address that is transmitted as part of an I2C packet. Only the

device that has a matching slave address responds to subsequent

I2C commands. Table 16 lists the supported device slave

addresses.

I2C Bus Characteristics

Table 21 provides a summary of the various I2C abbreviations

used in the protocol.

Table 21. I2C Bus Abbreviation Definitions

Abbreviation

Definition

Start

Repeated start

Stop

ACK

Acknowledge

NACK

No acknowledge

Write

Read

The transfer of data is shown in Figure 54. One clock pulse is

generated for each data bit transferred. The data on the SDA

line must be stable during the high period of the clock. The

high or low state of the data line can change only when the

clock signal on the SCL line is low.

Figure 54. Valid Bit Transfer

Start/stop functionality is shown in Figure 55. The start condition

is characterized by a high-to-low transition on the SDA line while

SCL is high. The start condition is always generated by the master

to initialize a data transfer. The stop condition is characterized

by a low-to-high transition on the SDA line while SCL is high.

The stop condition is always generated by the master to terminate

a data transfer. Every byte on the SDA line must be eight bits long.

Each byte must be followed by an acknowledge bit; bytes are sent

MSB first.

The acknowledge bit (ACK) is the ninth bit attached to any

8-bit data byte. An acknowledge bit is always generated by the

receiving device (receiver) to inform the transmitter that the

byte has been received. The acknowledge bit is communicated

by pulling the SDA line low during the ninth clock pulse after

each 8-bit data byte (see Figure 56).

The no acknowledge bit (

NACK

) is the ninth bit attached to any

8-bit data byte. The receiving device (receiver) always generates

the no acknowledge bit to inform the transmitter that the byte

has not been received. The no acknowledge bit is communi-

cated by leaving the SDA line high during the ninth clock pulse

after each 8-bit data byte.

DATA LINE

STABLE;

DATA VALID

CHANGE

OF DATA

ALLOWED

SDA

SCL

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