ADP5586ACBZ-01-R7 datasheet(15/44 Pages) AD

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Data Sheet

ADP5586

Rev. 0 | Page 15 of 44

RESET BLOCK

The ADP5586 features a reset block that can generate reset con-

ditions if certain events are detected simultaneously. Up to three

reset trigger events can be programmed for RESET_OUT. The

event scan control blocks monitor whether these events are

present for the duration of RESET_TRIG_TIME[3:0] (Register

0x2E, Bits[5:2]). If they are present, reset-initiate signals are sent

to the reset generator blocks. The generated reset signal pulse

width is programmable.

RESET_PULSE_WIDTH[1:0]

RESET_TRIG_TIME[3:0]

RESET_EVENT_A[7:0]

RESET_EVENT_B[7:0]

RESET_EVENT_C[7:0]

RST_PASSTHRU_EN

RST

(R4)

RESET_OUT

RESET_

INITIATE

RESET

GEN

KEY

SCAN

CONTROL

GPI

SCAN

CONTROL

LOGIC

BLOCK

CONTROL

Figure 20. Reset Blocks

The RESET_OUT signal uses the R4 I/O pin as its output,

which must be configured via the GPIO_5_OUT_EN bit

(Register 0x27, Bit 4) to enable the output function. A pass-

through mode also allows the RST pin function to be output on

the R4 pin.

The reset generation signals are useful in situations where the

system processor has locked up and the system is unresponsive

to input events. The user can press one of the reset event combi-

nations and initiate a system-wide reset, which eliminates the need

to remove the battery from the system and perform a hard reset.

The use of the immediate trigger time setting (see Table 55) is

recommended only in very low noise conditions with good

debounce; otherwise, false triggering may occur.

INTERRUPTS

The INT pin can be asserted low if any of the internal interrupt

sources is active. The user can select which internal interrupts

interact with the external interrupt pin in Register 0x3E (see

Table 71). Register 0x3D allows the user to choose whether the

external interrupt pin remains asserted, or deasserts for 50 μs

and then reasserts, as in the case where multiple internal

interrupts are asserted and one is cleared (see Table 70).

EVENT_INT

EVENT_IEN

INT DRIVE

INT

INT_CFG

GPI_INT

GPI_IEN

LOGIC_INT

LOGIC_IEN

OVRFLOW_INT

OVRFLOW_IEN

Figure 21. Asserting INT Low

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