AS6C3216 datasheet(9/13 Pages) ALSC

部件名	AS6C3216

功能描述	32M Bits ( 2Mx16 / 4Mx8 Switchable) LOW POWER CMOS SRAM

PDF	13 Pages

Scroll/Zoom	100%

制造商	ALSC [Alliance Semiconductor Corporation]

网页	https://www.alliancememory.com

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9 / 13 page

AS6C3216

Rev. 1.0

32M Bits ( 2Mx16 / 4Mx8 Switchable) LOW POWER CMOS SRAM

Alliance Memory, Inc.

WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6)

Dout

Din

Data Valid

tDW

tDH

(4)

High-Z

tWHZ

WE#

LB#,UB#

tCW

tAS

tWP

tBW

CE#

Address

tWR

tAW

tWC

CE2

Notes :

1.WE#,CE#, LB#, UB# must be high or CE2 must be low during all address transitions.

2.A write occurs during the overlap of a low CE#, high CE2, low WE#, LB# or UB# = low.

3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be

placed on the bus.

4.During this period, I/O pins are in the output state, and input signals must not be applied.

5.If the CE#, LB#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain

in a high impedance state.

6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.

AS6C3216 数据表(PDF) 9 Page - Alliance Semiconductor Corporation

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