ADP2386ACPZN-R7 datasheet(21/24 Pages) AD

21 / 24 page

Data Sheet

ADP2386

Rev. A | Page 21 of 24

CIRCUIT BOARD LAYOUT RECOMMENDATIONS

Good printed circuit board (PCB) layout is essential for obtaining

the best performance from the ADP2386. Poor PCB layout can

degrade the output regulation, as well as the electromagnetic

interference (EMI) and electromagnetic compatibility (EMC)

performance. Figure 36 shows an example of a good PCB layout

for the ADP2386. For optimum layout, refer to the following

guidelines:



Use separate analog ground planes and power ground

planes. Connect the ground reference of sensitive analog

circuitry, such as output voltage divider components, to

analog ground. In addition, connect the ground reference

of power components, such as input and output capacitors,

to power ground. Connect both ground planes to the

exposed GND pad of the ADP2386.



Place the input capacitor, inductor, and output capacitor as

close as possible to the IC, and use short traces.



Ensure that the high current loop traces are as short and as

wide as possible. Make the high current path from the input

capacitor through the inductor, the output capacitor, and the

power ground plane back to the input capacitor as short as

possible. To accomplish this, ensure that the input and output

capacitors share a common power ground plane.

In addition, ensure that the high current path from the power

ground plane through the inductor and output capacitor

back to the power ground plane is as short as possible by

tying the PGND pins of the ADP2386 to the PGND plane

as close as possible to the input and output capacitors.



Connect the exposed GND pad of the ADP2386 to a large,

external copper ground plane to maximize its power

dissipation capability and minimize junction temperature.

In addition, connect the exposed SW pad to the SW pins

of the ADP2386, using short, wide traces; or connect the

exposed SW pad to a large copper plane of the switching

node for high current flow.



Place the feedback resistor divider network as close as

possible to the FB pin to prevent noise pickup. Minimize

the length of the trace that connects the top of the feedback

resistor divider to the output while keeping the trace away

from the high current traces and the switching node to

avoid noise pickup. To further reduce noise pickup, place

an analog ground plane on either side of the FB trace and

ensure that the trace is as short as possible to reduce the

parasitic capacitance pickup.

ADP2386

BST

COMP

PGOOD

GND

SYNC

VREG

PGND

PVIN

VIN

CVREG

CIN

COUT

CBST

VOUT

RTOP

RBOT

CSS

Figure 35. High Current Path in the PCB Circuit

POWER GROUND PLANE

PVIN

VOUT

OUTPUT

CAPACITOR

INPUT

BULK

CAP

INPUT

BYPASS

CAP

INDUCTOR

GND

VREG

CVREG

CBST

COMP

PGND

GND

BST

PVIN

RTOP

RBOT

VIA

BOTTOM LAYER TRACE

ANALOG GROUND PLANE

COPPER PLANE

Figure 36. Recommended PCB Layout

ADP2386ACPZN-R7 数据表(PDF) 21 Page - Analog Devices

ADP2386ACPZN-R7 数据表(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

数据表下载

链接网址

ADP2386ACPZN-R7 数据表(PDF) 21 Page - Analog Devices

ADP2386ACPZN-R7 数据表(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

数据表 下载

链接网址

数据表下载