WM8903 datasheet(86/178 Pages) WOLFSON

86 / 178 page

WM8903

Production Data

PD, Rev 4.5, June 2012

BCLK FREQUENCY

The BCLK frequency is controlled relative to CLK_SYS by the BCLK_DIV divider. Internal clock divide

and phase control mechanisms ensure that the BCLK and LRC edges will occur in a predictable and

repeatable position relative to each other and relative to the data for a given combination of

DAC/ADC sample rate and BCLK_DIV settings.

BCLK_DIV is defined in the “Digital Audio Interface Control” section. See also the “Clocking and

Sample Rates” section for more information.

AUDIO DATA FORMATS (NORMAL MODE)

In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRC transition.

All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and

sample rate, there may be unused BCLK cycles after each LRC transition.

Figure 41 Right Justified Audio Interface (assuming n-bit word length)

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRC

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRC transition.

Figure 42 Left Justified Audio Interface (assuming n-bit word length)

In I

2S mode, the MSB is available on the second rising edge of BCLK following a LRC transition. The

other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency

and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of

the next.

WM8903 数据表(PDF) 86 Page - Wolfson Microelectronics plc