3.2 mm x 5.0 mm Ceramic Low Noise SMD VCXO,

LVCMOS / LVPECL / LVDS

I641 - Series

10/17/12_B

Specifications subject to change without notice

Page 1

Recommended Pad Layout

Dimension Units: mm

Pin

Connection

1

Voltage Control

2

Enable/Disable or N/C

3

GND

4

Output

5

Output or N/C

6

Frequency

LVCMOS

LVPECL

LVDS

10 MHz to 225 MHz

10 MHz to 1500 MHz

10 MHz to 1500 MHz

Output Level

LVCMOS

LVPECL

LVDS

VOH=90% VDD min., VOL=10 % VDD max.

VOH=VDD-1.03V max. (Nom. Load), VOL=VDD-1.6V max. (Nom. Load)

VOD=(Diff. Output) 350mV Typ.

Duty Cycle

LVCMOS

LVPECL

LVDS

50% ±5% @ 50%VDD

50% ±5% @ 50%*

50% ±5% @ 50%*

Rise / Fall Time

LVCMOS

LVPECL

LVDS

3.0 ns max. (90%/10%)*

0.6 ns max. (80%/20%)*

0.6 ns max. (80%/20%)*

Output Load

LVCMOS

LVPECL

LVDS

15pF

50

 to VDD - 2.0 VDC

RL=100

/CL=10pF

Frequency Stability

See Table Below

Supply Voltage

3.3 VDC ± 10%, 2.5VDC ± 5%

Current

LVCMOS = 25 mA max., LVPECL = 60 mA max., LVDS = 35 mA max.

Linearity

10% max.

Pullability

See Table Below

Control Voltage

1.65 VDC ± 1.65 VDC @ 3.3V

1.25 VDC ± 1.25 VDC @ 2.5V

Input Impedance

50K

 min.

Phase Jitter (RMS)

At 12kHz to 20 MHz

0.5 ps typical

Operating Temp.

Range

See Table Below

Storage

Part Number Guide

Sample Part Number:

I641–31AB9H2–155.520

Package

Input

Voltage

Operating

Temperature

Stability

(in ppm)

Pullabilty

Output

Enable / Disable

(Pin 2)

Complimentary

Ouput (Pin 5) **

Frequency

I641

3 = 3.3V

1 = 0

 C to +70 C

F =

20

B =

 50

3 = LVCMOS

H = Enable

1 = N.C.

-155.520 MHz

6 = 2.5V

3 = -20

 C to +70 C

A =

25

C =

100

8 = LVDS

O = N/C

2 = Output

2 = -40

 C to +85 C

B =

50

9 = LVPECL

Product Features

Applications

Small Surface Mount Package

xDSL

Ethernet/LAN/WAN

Low RMS Phase Jitter

Broadcast video

Optical modules

Frequencies to 1500 MHz

Wireless Base Stations

Clock and data recovery

Pb Free/ RoHS Compliant

Sonet /SDH

FPGA/ASIC

Leadfree Processing

WiMAX/WLAN

Backplanes

Server and Storage

GPON