MPC2002

•MPC2003

5

MOTOROLA FAST SRAM

EXTERNAL

ADDRESS

16

9

9

18

16

A15 – A2

DQ0 – DQ8

INTERNAL

ADDRESS

64K x 18

MEMORY

ARRAY

ADDRESS

REGISTERS

WRITE

REGISTER

ENABLE

REGISTER

DATA–IN

REGISTERS

OUTPUT

BUFFER

BAA

K

TSP

TSC

A15 – A0

UW

E

G

9

DQ9 – DQ17

9

9

9

LW

A0

′

A1

′

A1

LOAD

D1

BINARY

COUNTER

D0

Q1

Q0

BURST LOGIC

A0

NOTE:

All registers are positive–edge triggered. The TSC or TSP signals control the duration of the burst and the start of the next

burst. When TSP is sampled low, any ongoing burst is interrupted and a read (independent of W and TSC) is performed

using the new external address. Alternatively, a TSP–initiated two cycle WRITE can be performed by asserting TSP and

a valid address on the first cycle, then negating both TSP and TSC and asserting LW and/or UW with valid data on the se-

cond cycle (see Single Write Cycle in WRITE CYCLES timing diagram).

When TSC is sampled low (and TSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on

W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded. After

the first cycle of the burst, BAA controls subsequent burst cycles. When BAA is sampled low, the internal address is ad-

vanced prior to the operation. When BAA is sampled high, the internal address is not advanced, thus inserting a wait state

into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST

SEQUENCE GRAPH. Write refers to either or both byte write enables (LW, UW).

1,0

1,1

0,0

0,1

A1

′, A0′ =

NOTE: The external two values for A1 and A0

provide the starting point for the burst

sequence graph. The burst logic ad-

vances A1 and A0 as shown above.